Patent US3584209A successfully refreshed from Google Patents.
US3584209A
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Integrating analog memory
Assignee: United States Department of the Navy
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Filing: 1969-04-21
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Granted: 1971-06-08
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Expires: 1989-04-21
Abstract
Abstract An integrating analog memory circuit having a pair of switchable memory means for reading out memorized signals in one and combining with the new received signals for writing of the combined output into the other memory means, each input to the combining means being weighted, to detect a change by integration weighting means to detect a change in the mean energy level of new signals in a population of signals, many of which are varying as a result of amplitude modulation, and means for comparing the readout memory with the new signal to produce an alarm whenever the new signal exceeds the mean energy level of the memorized signal.
Inventors
- 👤 Ivan La-Garde
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-09 17:17
CPC Classifications
G; G06; G06G; G06G7/00; G06G7/12; G06G7/18
Claims Analysis
Total Claims: 5
Claim 1
Independent Claim
191 words
An analog integRation memory circuit comprising: first and second memory means, each having a read-in input and a readout output: a switch means in each input and output to alternately switch the input of one memory means with the output of the other memory means; an input of signals; a combiner having one input coupled to said input of signals, another input coupled to said switch means in the output of said memory means, and an output coupled to said switch means in the input of said memory means; first and second weighting networks in each of said one and other inputs of said combiner; and a comparator having one input coupled to said input of signals, a second input coupled to the switch means in the output of said memory means, said second input including means to proportion the readout memorized signal, and an output to produce an alarm signal whenever the one input signal exceeds said second input signal whereby input signals are compared with prior memorized readout signals and the sum and difference therefrom read in to said memory means to maintain a mean value of input signals.
Claim 2
Dependent Claim
191 words
An analog integRation memory circuit comprising: first and second memory means, each having a read-in input and a readout output: a switch means in each input and output to alternately switch the input of one memory means with the output of the other memory means; an input of signals; a combiner having one input coupled to said input of signals, another input coupled to said switch means in the output of said memory means, and an output coupled to said switch means in the input of said memory means; first and second weighting networks in each of said one and other inputs of said combiner; and a comparator having one input coupled to said input of signals, a second input coupled to the switch means in the output of said memory means, said second input including means to proportion the readout memorized signal, and an output to produce an alarm signal whenever the one input signal exceeds said second input signal whereby input signals are compared with prior memorized readout signals and the sum and difference therefrom read in to said memory means to maintain a mean value of input signals.
Claim 3
Dependent Claim
23 words
An analog integrating memory circuit as set forth in claim 1 wherein said first and second memory means are electron beam storage tubes.
Claim 4
Dependent Claim
46 words
An analog integrating memory circuit as set forth in claim 2 wherein said inputs to said first weighting means and to said comparator each includes a lin-log converter network to convert the input signals to intermediate levels suited to the dynamic range of the input signals.
Claim 5
Dependent Claim
41 words
An analog integrating memory as set forth in claim 3 wherein said signal input is switched and coupled to said switching means to switch said signal input for an input of signal for each alternate switching operation of said switching means.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1974-06-07 | 1974-12-07 | 1975-06-08 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1978-06-07 | 1978-12-07 | 1979-06-08 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1982-06-07 | 1982-12-07 | 1983-06-08 | $7700.00 | Window Closed / Lapsed |