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Patent US3584200A successfully refreshed from Google Patents.
US3584200A
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Method and apparatus for serial shift register coding
Assignee: General Electric Co
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Filing: 1968-02-29
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Granted: 1971-06-08
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Expires: 1988-02-29
Abstract
Abstract An arrangement for using a shift register to represent movement of a monitored item wherein switching of successive stages of the register indicates movement of a predetermined magnitude and wherein interpolation data is also selectively stored in the register to indicate quantities between said predetermined magnitude.
Inventors
- 👤 John D Layman
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-29 10:39
CPC Classifications
B; B65; B65G; B65G43/00; B65G2811/00; B65G2811/06; B65G2811/0673
Claims Analysis
Total Claims: 13
Claim 1
Independent Claim
156 words
In combination a source of recurrent control pulses, a shift register, means responsive to said recurrent control pulses to provide recurrent shift pulses having a longer period than said control pulses, means to set a stage in said shift register representing an event means to provide data defining in time the setting of said shift register including means to count the number of control pulse periods following a preceding shift pulse occurrence, means for entering said data into said shift register in the stages following the event stage, means responsive to said shift pulses to shift said event stage setting and said entered data along said shift register, and means for reading said event stage setting and said entered data at a later time to provide a signal representing the same number of control pulse periods following a point in time corresponding to a given number of control pulse periods after said preceding shift pulse occurrence.
Claim 2
Dependent Claim
156 words
In combination a source of recurrent control pulses, a shift register, means responsive to said recurrent control pulses to provide recurrent shift pulses having a longer period than said control pulses, means to set a stage in said shift register representing an event means to provide data defining in time the setting of said shift register including means to count the number of control pulse periods following a preceding shift pulse occurrence, means for entering said data into said shift register in the stages following the event stage, means responsive to said shift pulses to shift said event stage setting and said entered data along said shift register, and means for reading said event stage setting and said entered data at a later time to provide a signal representing the same number of control pulse periods following a point in time corresponding to a given number of control pulse periods after said preceding shift pulse occurrence.
Claim 3
Independent Claim
214 words
A method of coding a plural stage shift register comprising producing first pulses having a first recurrence rate, producing second pulses having a second recurrence rate, said first rate having an integral relationship with said second rate, entering data representing a given timed event which is independent of the occurrence time of said first and second pulses into at least one given stage of said register, generating a coded representation of the number of first pulses produced between the time of entering of said data into said at least one stage and the occurrence time of the previously produced second pulse, entering said coded representation into at least one stage of said register following said at least one given stage in the direction of shifting of said register, shifting in response to said second pulses said entered data and entered coded representation through stages of said register simultaneously at said second recurrence rate, detecting said entered data after having bEen shifted to at least one subsequent stage of the register, detecting, in response to said detection of said entered data, said entered coded representation after having been shifted to at least one subsequent stage of the register, converting said detected coded representation into a corresponding numerical number representation, and utilizing said numerical number representation.
Claim 4
Independent Claim
214 words
A method of coding a plural stage shift register comprising producing first pulses having a first recurrence rate, producing second pulses having a second recurrence rate, said first rate having an integral relationship with said second rate, entering data representing a given timed event which is independent of the occurrence time of said first and second pulses into at least one given stage of said register, generating a coded representation of the number of first pulses produced between the time of entering of said data into said at least one stage and the occurrence time of the previously produced second pulse, entering said coded representation into at least one stage of said register following said at least one given stage in the direction of shifting of said register, shifting in response to said second pulses said entered data and entered coded representation through stages of said register simultaneously at said second recurrence rate, detecting said entered data after having bEen shifted to at least one subsequent stage of the register, detecting, in response to said detection of said entered data, said entered coded representation after having been shifted to at least one subsequent stage of the register, converting said detected coded representation into a corresponding numerical number representation, and utilizing said numerical number representation.
Claim 5
Dependent Claim
39 words
The method according to claim 2 further comprising the step of inhibiting the further detection of said coded representation until said entered coded representation has been shifted beyond said at least said first-mentioned one subsequent stage of said register.
Claim 6
Dependent Claim
36 words
The method according to claim 2 further comprising the step of entering said coded representation and said data representing a given timed event into said register during the same time period between successive first rate pulses.
Claim 7
Dependent Claim
206 words
In combination, a plural stage shift register, means for providing first pulses having a first recurrence rate, means for providing second pulses having a second recurrence rate which is a submultiple of said first recurrence rate, means for entering data representing a given timed event which is independent of the occurrence time of said first and second pulses into at least one given stage of said register, means for generating a coded representation of the number of first pulses produced between the time of entering of said data into said at least one stage and the occurrence time of the previously produced second pulse, means for entering said coded representation into stages of said register following said at least one given stage in the direction of shifting of said register, means responsive to said second pulses for shifting said entered data and entered coded representation through stages of said register simultaneously at said second recurrence rate, means for detecting said entered data after having been shifted to a subsequent stage of the register, means responsive to said detection of said entered data for reading said entered coded representation after having been shifted to subsequent stages of the register, and means for utilizing said read coded representation.
Claim 8
Dependent Claim
206 words
In combination, a plural stage shift register, means for providing first pulses having a first recurrence rate, means for providing second pulses having a second recurrence rate which is a submultiple of said first recurrence rate, means for entering data representing a given timed event which is independent of the occurrence time of said first and second pulses into at least one given stage of said register, means for generating a coded representation of the number of first pulses produced between the time of entering of said data into said at least one stage and the occurrence time of the previously produced second pulse, means for entering said coded representation into stages of said register following said at least one given stage in the direction of shifting of said register, means responsive to said second pulses for shifting said entered data and entered coded representation through stages of said register simultaneously at said second recurrence rate, means for detecting said entered data after having been shifted to a subsequent stage of the register, means responsive to said detection of said entered data for reading said entered coded representation after having been shifted to subsequent stages of the register, and means for utilizing said read coded representation.
Claim 9
Independent Claim
149 words
A system for coding a shift register comprising means for generating recurring shift pulses, means for generating a plurality of interpolation pulses occurring between recurring shift pulses, means for setting a marker signal in a given stage of said register, means for deriving a coded representation of the number of interpolation pulses that were generated since the occurrence of the preceding shift pulse and the time of setting of said marker signal in said given stage of said register, means operative upon the setting of said given stage to set said coded representation into a plurality of stages of said register following said given stage, means for simultaneously shifting said set marker signal and said set coded representation through a plurality of said shift register stages, and means for utilizing said set data and said coded representation after having been shifted through a plurality of stages of said register.
Claim 10
Independent Claim
149 words
A system for coding a shift register comprising means for generating recurring shift pulses, means for generating a plurality of interpolation pulses occurring between recurring shift pulses, means for setting a marker signal in a given stage of said register, means for deriving a coded representation of the number of interpolation pulses that were generated since the occurrence of the preceding shift pulse and the time of setting of said marker signal in said given stage of said register, means operative upon the setting of said given stage to set said coded representation into a plurality of stages of said register following said given stage, means for simultaneously shifting said set marker signal and said set coded representation through a plurality of said shift register stages, and means for utilizing said set data and said coded representation after having been shifted through a plurality of stages of said register.
Claim 11
Dependent Claim
56 words
A system for coding a shift register according to claim 6 wherein said means for deriving and said means for setting said coded representation comprises a counter, means for supplying said interpolation pulses to said counter, and means for registering the count level of said counter in said following stages when said given stage is set.
Claim 12
Dependent Claim
88 words
A system for coding a shift register according to claim 7, wherein said means for utilizing comprises means connected to detect the occurrence of said marker signal after having been shifted to a succeeding stage of said register, a counter, means for setting said last-named counter when said shifted marker signal is detected in accordance with the states of the stages representing said coded representation and following said succeeding stage, and means for producing an output signal related to the time of occurrence of said preceding shift pulse.
Claim 13
Dependent Claim
50 words
A System according to claim 8 wherein the detection means includes means for automatically inhibiting operation thereof after a set condition is detected, for a period of time commensurate with the number of shift pulses needed to shift out all of the coded representation information appearing in the following stages.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1974-06-07 | 1974-12-07 | 1975-06-08 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1978-06-07 | 1978-12-07 | 1979-06-08 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1982-06-07 | 1982-12-07 | 1983-06-08 | $7700.00 | Window Closed / Lapsed |