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US3582973A
Expired / Lapsed
US
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A high-speed bistable switching circuits
Assignee: The General Electric Company PLC
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Filing: 1968-11-29
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Granted: 1971-06-01
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Expires: 1988-11-29
Abstract
Abstract A two-state transistor circuit particularly for operation at high speeds in which switching pulses are repeatedly steered to one or other of two switching transistors. Repeated ''switching'' to the same state, as in a 111111 pulse sequence, tends to build up a charge which delays a change of state when it eventually occurs (1111110). Two diodes connected back to back between the switching pulse electrodes of the transistors limit the charge accumulation and hasten the eventual state change. A resistor connected between the electrodes is an inferior alternative.
Inventors
- 👤 Richard Munro Dorward
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-27 18:16
CPC Classifications
H; H03; H03K; H03K3/00; H03K3/01; H03K3/012; H04; H04B; H04B14/00; H04B14/02; H04B14/04; H04B14/042
Claims Analysis
Total Claims: 3
Claim 1
Independent Claim
239 words
A bistable circuit having independent steering and driving inputs and comprising: A. two transistors having i. emitter, base and collector electrodes, B. a first potential source terminal, C. circuit means connecting each collector electrode to said first potential source terminal, D. resistive circuit means connecting each collector electrode to the base electrode of the other transistor, E. circuit means directly connecting the emitter electrodes to one another, F. a second potential source terminal, G. a common emitter resistor connected between said emitter electrodes and said second potential source terminal, H. a respective bias circuit connected to each base electrode and cooperating with said common emitter resistor for limiting the conducting state of each transistor to a nonsaturated condition, I. a current pulse generator for producing drive pulses of limited magnitude, J. a steering circuit connected to said current-pulse generator for receiving said drive pulses and being responsive to a steering signal to steer a received drive pulse to one or the other of two outputs in dependence upon said steering signal, K. circuit means connecting said two outputs to said base electrodes respectively to supply a drive pulse for establishing a predetermined conduction state of the associated transistor, and L. two semiconductor diodes connected in parallel and in opposite directions between said base electrodes for limiting the differential accumulation of charge on said two base electrodes when a plurality of successive drive pulses are steered to the same transistor.
Claim 2
Dependent Claim
239 words
A bistable circuit having independent steering and driving inputs and comprising: A. two transistors having i. emitter, base and collector electrodes, B. a first potential source terminal, C. circuit means connecting each collector electrode to said first potential source terminal, D. resistive circuit means connecting each collector electrode to the base electrode of the other transistor, E. circuit means directly connecting the emitter electrodes to one another, F. a second potential source terminal, G. a common emitter resistor connected between said emitter electrodes and said second potential source terminal, H. a respective bias circuit connected to each base electrode and cooperating with said common emitter resistor for limiting the conducting state of each transistor to a nonsaturated condition, I. a current pulse generator for producing drive pulses of limited magnitude, J. a steering circuit connected to said current-pulse generator for receiving said drive pulses and being responsive to a steering signal to steer a received drive pulse to one or the other of two outputs in dependence upon said steering signal, K. circuit means connecting said two outputs to said base electrodes respectively to supply a drive pulse for establishing a predetermined conduction state of the associated transistor, and L. two semiconductor diodes connected in parallel and in opposite directions between said base electrodes for limiting the differential accumulation of charge on said two base electrodes when a plurality of successive drive pulses are steered to the same transistor.
Claim 3
Dependent Claim
54 words
A shift register comprising a plurality of stages each comprising a bistable circuit according to claim 1, the stages being interconnected so as to cycle a digital pattern which includes a succession of the same digit thus causing a said plurality of drive pulses to be steered to the same transistor in any stage.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1974-05-31 | 1974-11-30 | 1975-06-01 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1978-05-31 | 1978-11-30 | 1979-06-01 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1982-05-31 | 1982-11-30 | 1983-06-01 | $7700.00 | Window Closed / Lapsed |