Direct coupled differential transistor amplifier with improved common mode performance

Claim 2

A differential amplifier having high common mode rejection characteristics comprising: first and second amplifier means connected in a differential configuration, each of said amplifier means having an input terminal and an output terminal, means for impressing first and second signals upon the input terminals of said first and second amplifier means, respectively, means connected to both said amplifier means for deriving a common mode signal, a floating power supply connected to the output terminals of said first and second amplifiers, and means for coupling said common mode signal to said power supply to drive each side of the power supply in a direction to minimize the common mode signal and simultaneously keep the voltage drop across each amplifying means constant.

Claim 3

A differential amplifier for amplifying the differential mode of a pair of input signals while simultaneously suppressing any common mode signal appearing therewith comprising: first and second transistors connected in a differential configuration, each of said transistors having base, emitter and collector electrodes, means for impressing the first and second input signals, each of which is accompanied by a common mode signal, upon said base electrodes of said first and second transistors, respectively, means connected to said collector electrodes of said first and second transistors for driving the common mode signal, load impedance means in the collector circuit of said first and second transistors for deriving a differential output signal, a floating power supply, first means for connecting said power supply to said collector electrodes of each of said first and second transistors through said load impedance means, and means connected to said common mode signal deriving means for coupling said common mode signal to said floating power supply to drive the magnitude of the voltage appearing on said first means in a direction so as to minimize the common mode signal while simultaneously keeping the collector to emitter voltage of each transistor constant.

Claim 4

A differential amplifier for amplifying the differential mode of a pair of input signals while simultaneously suppressing any common mode signal appearing therewith comprising: first and second transistors connected in a differential configuration, each of said transistors having base, emitter and collector electrodes, means for impressing the first and second input signals, each of which is accompanied by a common mode signal, upon said base electrodes of said first and second transistors, respectively, means connected to said collector electrodes of said first and second transistors for driving the common mode signal, load impedance means in the collector circuit of said first and second transistors for deriving a differential output signal, a floating power supply, first means for connecting said power supply to said collector electrodes of each of said first and second transistors through said load impedance means, and means connected to said common mode signal deriving means for coupling said common mode signal to said floating power supply to drive the magnitude of the voltage appearing on said first means in a direction so as to minimize the common mode signal while simultaneously keeping the collector to emitter voltage of each transistor constant.

Claim 5

A differential amplifier as defined in claim 7 wherein said power supply comprises: a constant current source, and a voltage dividing means connected to said constant current source and between said first means and said coupling means wherein the current supplied by said constant current source flows through said voltage dividing means to provide a predetermined bias voltage.

Claim 6

A differential amplifier as defined in claim 2 wherein said means for deriving the common mode signal comprises a resistive summing network connected to the collector electrodes of said first and second transistors.

Claim 7

A differential amplifier as defined in claim 4 wherein said coupling means includes an amplifier connected between said resistive summing network and the emitter electrodes of said first and second transistors for coupling said common signal to said emitter electrodes.

Claim 8

A differential amplifier for amplifying the differential mode of first and second input signals while simultaneously suppressing common mode signals accompanying said input signals and whose amplitude varies with respect to a selected reference point comprising: first and second transistors connected in a differential configuration, each of said transistors having base, emitter and collector electrodes, said first input signal being impressed upon the base electrode of said first transistor and said second input signal being impressed upon the base electrode of said second transistor, load impedance means connected to said collector electrodes of said first and second transistors across which a differential output signal is developed, first means connected to said emitter electrodes of said first and second transistors to derive the common mode signal, a floating power supply, connecting means for connecting one side of said floating power supply to the collector electrodes of each of said transistors through the load impedance means, means connected between said first common mode signal deriving means and said floating power supply to couple the common mode signal to the other side of the floating power supply to drive the voltage appearing on said connecting means with respect to said reference point in a direction to minimize the common mode signal while simultaneously keeping the collector to emitter voltage across each transistor constant.

Claim 9

A differential amplifier for amplifying the differential mode of first and second input signals while simultaneously suppressing common mode signals accompanying said input signals and whose amplitude varies with respect to a selected reference point comprising: first and second transistors connected in a differential configuration, each of said transistors having base, emitter and collector electrodes, said first input signal being impressed upon the base electrode of said first transistor and said second input signal being impressed upon the base electrode of said second transistor, load impedance means connected to said collector electrodes of said first and second transistors across which a differential output signal is developed, first means connected to said emitter electrodes of said first and second transistors to derive the common mode signal, a floating power supply, connecting means for connecting one side of said floating power supply to the collector electrodes of each of said transistors through the load impedance means, means connected between said first common mode signal deriving means and said floating power supply to couple the common mode signal to the other side of the floating power supply to drive the voltage appearing on said connecting means with respect to said reference point in a direction to minimize the common mode signal while simultaneously keeping the collector to emitter voltage across each transistor constant.

Claim 10

A differential amplifier as defined in claim 6 comprising in addition second means coupled to the collector electrodes of said first and second transistors to derive the common mode signal and amplifier means connected between said second means and said emitter electrodes of said first and second transistors and responsive to said common mode signal to vary the collector current in said first and second transistors to compensate for the common mode signal.

Claim 11

A differential amplifier as defined in claim 7 wherein said floating power supply comprises a constant current source and a voltage dividing means connected to said constant current source and between said connecting means and said common mode signal coupling means.

Claim 12

A differential amplifier as defined in claim 2 wherein said means for deriving a common mode signal comprises a Resistive summing network connected to the emitter electrodes of said first and second transistors.

Claim 13

A differential amplifier as defined in claim 9 wherein said coupling means comprises an emitter follower circuit connected between said resistive summing network and one side of said floating power supply.

Claim 14

A multistage differential amplifier for amplifying the differential mode of first and second input signals while simultaneously suppressing common mode signals accompanying said input signals comprising: first and second differential amplifier stages, each stage comprising first and second transistors connected in a differential configuration, each of said transistors having base, emitter and collector electrodes, said first input signal being impressed upon the base electrode of said first transistor in said first stage and said second input signal being impressed upon the base electrode of said second transistor in said first stage, load impedance means connected to said collector electrodes of said first and second transistors of each stage across which a differential output signal is developed, means for connecting the collector electrodes of said first and second transistors in said first stage to the base electrodes of said first and second transistors, respectively, in said second stage, first common mode signal deriving means connected to said emitter electrodes of said first and second transistors of said first stage to derive the common mode signal, a floating power supply, a first means for connecting said floating power supply to the collector electrodes of each of said transistors in each stage through the load impedance means, a second means for connecting said floating power supply to said emitter electrodes of each of said transistors in said second stage, and means connected between said first common mode signal deriving means and said floating power supply to couple the common mode signal to said second connecting means to drive each side of the power supply in the same direction to minimize the common mode signal while simultaneously maintaining the collector to emitter voltage across each transistor in each stage constant.

Claim 15

A multistage differential amplifier for amplifying the differential mode of first and second input signals while simultaneously suppressing common mode signals accompanying said input signals comprising: first and second differential amplifier stages, each stage comprising first and second transistors connected in a differential configuration, each of said transistors having base, emitter and collector electrodes, said first input signal being impressed upon the base electrode of said first transistor in said first stage and said second input signal being impressed upon the base electrode of said second transistor in said first stage, load impedance means connected to said collector electrodes of said first and second transistors of each stage across which a differential output signal is developed, means for connecting the collector electrodes of said first and second transistors in said first stage to the base electrodes of said first and second transistors, respectively, in said second stage, first common mode signal deriving means connected to said emitter electrodes of said first and second transistors of said first stage to derive the common mode signal, a floating power supply, a first means for connecting said floating power supply to the collector electrodes of each of said transistors in each stage through the load impedance means, a second means for connecting said floating power supply to said emitter electrodes of each of said transistors in said second stage, and means connected between said first common mode signal deriving means and said floating power supply to couple the common mode signal to said second connecting means to drive each side of the power supply in the same direction to minimize the common mode signal while simultaneously maintaining the collector to emitter voltage across each transistor in each stage constant.

Claim 16

A multistage differential amplifier as defined in claim 11 comprising in addition a second common signal deriving means connected to said collector electrodes of said first and second transistors in said second stage to derive the common mode signal and amplifier means connected between said second common mode signal deriving means and said emitter electrodes of said first and second transistors in said first stage.