Patent US3582789A successfully refreshed from Google Patents.
US3582789A
Expired / Lapsed
US
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Asynchronous data signal reception
Assignee: Motorola Solutions Inc
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Filing: 1969-01-21
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Granted: 1971-06-01
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Expires: 1989-01-21
Abstract
Abstract An incoming digital signal having a pulse repetitive frequency within a given range of frequencies is compared with multiplephase clock signals, all within such given range of frequencies. In the receiver, a plurality of channels, one channel for each phase of the multiphase clock source, are jointly responsive to the incoming digital signal and to any one of the phases to actuate the channel to an active condition and simultaneously inhibit all other channels from being jointly responsive to such digital signal and respective clock phase. Upon completion of receipt of a predetermined number of digital signals, the receiver is reset to again permit any channel to be jointly responsive to an incoming digital signal and any clock phase for actuating a channel. Detection of incoming digital signals by a channel in an active condition includes comparing the incoming digital signal with a clock phase other than the clock phase used to activate the channel. Such other clock phase is selected on the basis of a change of signal state of the incoming digital signal. The resultant detected signal is then supplied to a data processing circuit.
Inventors
- 👤 John R Mick
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-26 07:05
CPC Classifications
H; H04; H04L; H04L7/00; H04L7/02; H04L7/033; H04L7/0337; H04L7/0338; H04L5/00; H04L5/02; H04L5/12; H04L5/22; H04L5/24; H04L5/245
Claims Analysis
Total Claims: 7
Claim 1
Independent Claim
241 words
A receiver system for use in a digital communication network for asynchronously receiving digital data signals, each having a given bit time within a predetermined range of frequencies, the improved receiver including the combination, a multiphase clock source having a frequency stability such that its fundamental frequency resides in said predetermined range of frequencies and for producing a plurality of clock signals during each said given bit times and each phase having an activating portion, a plurality of data signal processing and latching channels each for receiving incoming digital data signals, one channel for each of said phases generated by said multiphase clock source, each channel receiving one of said phases and jointly responsive to an incoming data signal and an activating portion as a clock phase signal for generating a latch signal, bistable means responsive to said latch signal for generating an active condition, a lockout signal inductive of said active condition for each of said respective channels being supplied by such channel to each and every other channel for inhibiting responsiveness of such channel to incoming data signals, gating means in each channel jointly responsive to incoming data signals, one of said clock phase activating portions and to said bistable means being in an active condition to supply a signal indicative of the incoming data signals, and signal combining means connected to all of said channels for receiving such output signals for generating a train of a data signal.
Claim 2
Dependent Claim
241 words
A receiver system for use in a digital communication network for asynchronously receiving digital data signals, each having a given bit time within a predetermined range of frequencies, the improved receiver including the combination, a multiphase clock source having a frequency stability such that its fundamental frequency resides in said predetermined range of frequencies and for producing a plurality of clock signals during each said given bit times and each phase having an activating portion, a plurality of data signal processing and latching channels each for receiving incoming digital data signals, one channel for each of said phases generated by said multiphase clock source, each channel receiving one of said phases and jointly responsive to an incoming data signal and an activating portion as a clock phase signal for generating a latch signal, bistable means responsive to said latch signal for generating an active condition, a lockout signal inductive of said active condition for each of said respective channels being supplied by such channel to each and every other channel for inhibiting responsiveness of such channel to incoming data signals, gating means in each channel jointly responsive to incoming data signals, one of said clock phase activating portions and to said bistable means being in an active condition to supply a signal indicative of the incoming data signals, and signal combining means connected to all of said channels for receiving such output signals for generating a train of a data signal.
Claim 3
Dependent Claim
23 words
The subject matter of claim 1 wherein said one clock phase activating portion occurs approximately in the middle of said given bit time.
Claim 4
Dependent Claim
219 words
A digital data detection system for detecting digital signals from a plurality of sources and having substantially the same repetitive frequency with a given bit of time but asynchronous as to phase, the improvement including the combination, a multiphase clock source supplying a plurality of clock signals of different phase, each having an activating portion each of said given bit times, a like plurality of signal processing channels for receiving said digital signals and each signal processing channel receiving a different one of said clock signals and jointly responsive thereto to initiate an active condition therein for detecting said digital signals, all of said signal processing channels being responsive to said active condition in any other of said signal processing channel to inhibit its respective joint response such that one and only one signal processing channel is in said active condition at a given time, and each one of said activating portions of said clock signals having a phase relationship to at least one other of said activating portions equal to about one-half said given bit time such that said one other activating portions occurs about midway of bit times beginning about the time of occurrence of the respective each one of said activating portions and said one other activating portions being said different one of said clock signals.
Claim 5
Dependent Claim
219 words
A digital data detection system for detecting digital signals from a plurality of sources and having substantially the same repetitive frequency with a given bit of time but asynchronous as to phase, the improvement including the combination, a multiphase clock source supplying a plurality of clock signals of different phase, each having an activating portion each of said given bit times, a like plurality of signal processing channels for receiving said digital signals and each signal processing channel receiving a different one of said clock signals and jointly responsive thereto to initiate an active condition therein for detecting said digital signals, all of said signal processing channels being responsive to said active condition in any other of said signal processing channel to inhibit its respective joint response such that one and only one signal processing channel is in said active condition at a given time, and each one of said activating portions of said clock signals having a phase relationship to at least one other of said activating portions equal to about one-half said given bit time such that said one other activating portions occurs about midway of bit times beginning about the time of occurrence of the respective each one of said activating portions and said one other activating portions being said different one of said clock signals.
Claim 6
Dependent Claim
205 words
The subject matter of claim 3 wherein each said signal processing channel supplies a lockout signal having inactive and active condition signal states indicating the deactivation or activation respectively of said signal processing channel, each channel having input coincidence means receiving said digital signals, a respective one of said clock signals and said lockout signal from all other channels and responsive to any one of said lockout signals indicating an active condition to become nonresponsive to any other of said received signals and when all said lockout signals indicating an inactive condition being jointly responsive to said respective one of said clock signals and one of said digital signals to supply a channel activating signal, means in each said signal processing channel responsive to said respective activating signals to initiate an active condition therein and cause a lockout signal to be in said Active condition signal state, and gating means in each said signal processing channel jointly responsive to said active condition signal state, said different one of said clock signals and to said digital signals in the respective one of said signal processing channel to supply a train of gated digital signals in synchronism with said clock signals and indicative of said digital signals.
Claim 7
Dependent Claim
108 words
The subject matter of claim 4 further including counting means for counting a predetermined number of digital signals, detector means receiving all said lockout signals and responsive to any one of said lockout signals in said active condition signal state to supply a gate enabling signal, gating means receiving a synchronizing one of said clock signals and responsive to said gate enabling signal to pass said synchronizing one clock signal to said counting means, and said counting means being responsive to said predetermined number of said synchronizing clock signals to supply a reset latch signal to all said signal processing channels for resetting same to said inactive conditions.
References Cited (Backward Citations)
US2845613A
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1974-05-31 | 1974-11-30 | 1975-06-01 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1978-05-31 | 1978-11-30 | 1979-06-01 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1982-05-31 | 1982-11-30 | 1983-06-01 | $7700.00 | Window Closed / Lapsed |