US3582786A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Transmission check in data system
Assignee: Automatic Electric Laboratories Inc
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Filing: 1968-05-22
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Granted: 1971-06-01
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Expires: 1988-05-22
Abstract
Abstract A diphase signaling system wherein the signal equipment is arranged to send a confirming signal for every signal received and further having a small shift register connected to the sending and receiving equipment in such a way that it can be shifted in both directions. At the sending station, every time that a bit ''''1'''' is sent the register is shifted in a first direction. The receiving station upon detecting the bit ''''1'''' replies with an identical signal via the other path to the sending station, where this confirming signal is detected and applied to the shift register to erase the previously recorded bit. Upon the completion of the sending of data from the first to the second station and the receipt of a confirmation for each bit of data sent the shift register should be in a completely reset or empty state, indicative of the fact that the data sent was correctly received by the receiving station.
Inventors
- 👤 Lucas Bruglemans
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-24 11:23
CPC Classifications
H; H04; H04L; H04L1/00; H04L1/12; H04L1/14
Claims Analysis
Total Claims: 7
Claim 1
Independent Claim
277 words
In a system for transmitting data in a binary system of notation in which two transceivers are connected by a first and a second pair of transmission lines, each said transceiver including means for generating a carrier signal, synchronizing means for generating synchronizing pulses, modulating means, demodulating means, a shift register and a common control means; means for placing a first one of said transceivers in a send mode in which its synchronizing pulse drive its shift register to operate its modulating means so that a transmitter carrier signal is modulated in accordance with the data from its shift register and applied to said first pair of transmission lines, means for placing the other one of said transceivers in a receive mode in which its demodulating means is operated in response to the synchronizing pulses and said modulated signal received via said first pair of transmission lines to serially transfer into its associated shift register the derived data; a binary counter in said first transceiver, simultaneously responsive to said transmitted data signal and to said received confirmation data signal and operated to increment a count for each data bit shifted from said shift register and binary means at said other transceiver actuated to operate said associated modulator to return a confirmation bit via said second pair of transmission lines for each bit transferred into its associated shift register, said demodulator at said first one of said transceivers operated in response to said confirmation bit and its synchronizing pulses to operate said binary counter to decrement a count for each confirmation bit, whereby upon completed transmission and confirmation reception of data said counter is in its original state.
Claim 2
Dependent Claim
277 words
In a system for transmitting data in a binary system of notation in which two transceivers are connected by a first and a second pair of transmission lines, each said transceiver including means for generating a carrier signal, synchronizing means for generating synchronizing pulses, modulating means, demodulating means, a shift register and a common control means; means for placing a first one of said transceivers in a send mode in which its synchronizing pulse drive its shift register to operate its modulating means so that a transmitter carrier signal is modulated in accordance with the data from its shift register and applied to said first pair of transmission lines, means for placing the other one of said transceivers in a receive mode in which its demodulating means is operated in response to the synchronizing pulses and said modulated signal received via said first pair of transmission lines to serially transfer into its associated shift register the derived data; a binary counter in said first transceiver, simultaneously responsive to said transmitted data signal and to said received confirmation data signal and operated to increment a count for each data bit shifted from said shift register and binary means at said other transceiver actuated to operate said associated modulator to return a confirmation bit via said second pair of transmission lines for each bit transferred into its associated shift register, said demodulator at said first one of said transceivers operated in response to said confirmation bit and its synchronizing pulses to operate said binary counter to decrement a count for each confirmation bit, whereby upon completed transmission and confirmation reception of data said counter is in its original state.
Claim 3
Dependent Claim
38 words
Apparatus in accordance with claim 1 further including a trouble recording means operated in response to said counter advancing to a predetermined count indicative of the number of data bits transmitted exceeding the number of confirmation bits received.
Claim 4
Dependent Claim
72 words
Apparatus in accordance with claim 1 wherein said binary counter at said first transceiver comprises first and second bistable devices, so arranged that said first device is placed in a second set state in response to a first set pulse and said second device is placed in a second set state in response to a second set pulse, said set pulses each corresponding to a data bit shifted from said shift register.
Claim 5
Dependent Claim
65 words
Apparatus in accordance with claim 3 wherein said binary counter is further arranged to return said second device to said first stable state in response to a first reset pulse and to return said first devicE to said first stable state in response to a second reset pulse, said reset pulses each corresponding to a confirmation bit received via said second pair of transmission lines.
Claim 6
Dependent Claim
42 words
Apparatus in accordance with claim 4 further including trouble recording means, and means operative in response to the set condition of said first and second bistable devices during sending and the presence of a reset pulse to set said trouble recording means.
Claim 7
Dependent Claim
50 words
Apparatus in accordance with claim 4 further including trouble recording means and means operative in response to the set condition of either said first or second bistable device during sending and the receipt of an end of message signal from said common control means to set said trouble recording means.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1974-05-31 | 1974-11-30 | 1975-06-01 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1978-05-31 | 1978-11-30 | 1979-06-01 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1982-05-31 | 1982-11-30 | 1983-06-01 | $7700.00 | Window Closed / Lapsed |