Patent US2774342A successfully refreshed from Google Patents.
Patent US3582686A successfully refreshed from Google Patents.
US3582686A
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Reset circuit for a multistage counter
Assignee: Raytheon Co
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Filing: 1969-12-16
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Granted: 1971-06-01
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Expires: 1989-12-16
Abstract
Abstract A reset circuit for a multistage counter of the type clockable by clock pulses, successively applied on two clock lines, includes two MOS FET''s which, when rendered conductive by the application of an appropriate potential to their gate electrodes, effectively electrically connect the clock lines to a potential supplying terminal, thereby applying a clocking potential to the lines. The circuit includes a third MOS FET, which is used to apply a logic 0 level to the input terminal of the first counter stage. The respective gate electrodes of the three MOS FET''s are connected to a reset line so that a reset pulse on this line activates the three MOS FET''s.
Inventors
- 👤 Carroll R Perkins
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-29 22:34
CPC Classifications
H; H03; H03K; H03K21/00; H03K21/38
Claims Analysis
Total Claims: 5
Claim 1
Independent Claim
192 words
In combination with a multistage counter in which each stage is successively clockable by a first clock pulse supplied thereto on a first clock line and by a second clock pulse supplied thereto on a second clock line, so as to shift binary data from one stage section to the next stage section and from one stage to the next succeeding stage, an arrangement for resetting said stages comprising: first and second metal oxide semiconductor field effect transistors, each having a first electrode, a second electrode, and a control electrode; means for connecting the respective first electrodes Of said first and second transistors to said first and second clock lines, respectively; means for applying to the second electrode of each of said first and second transistors a level of potential which when applied to said clock lines results in the clocking of said stages so as to shift data therein; and means for applying a reset pulse to the control electrode of each of said first and second transistors to render said first and second transistors conductive of current to effectively apply said potential level to said first and second clock lines.
Claim 2
Dependent Claim
192 words
In combination with a multistage counter in which each stage is successively clockable by a first clock pulse supplied thereto on a first clock line and by a second clock pulse supplied thereto on a second clock line, so as to shift binary data from one stage section to the next stage section and from one stage to the next succeeding stage, an arrangement for resetting said stages comprising: first and second metal oxide semiconductor field effect transistors, each having a first electrode, a second electrode, and a control electrode; means for connecting the respective first electrodes Of said first and second transistors to said first and second clock lines, respectively; means for applying to the second electrode of each of said first and second transistors a level of potential which when applied to said clock lines results in the clocking of said stages so as to shift data therein; and means for applying a reset pulse to the control electrode of each of said first and second transistors to render said first and second transistors conductive of current to effectively apply said potential level to said first and second clock lines.
Claim 3
Dependent Claim
58 words
The arrangement as recited in claim 1 further including a third metal oxide semiconductor field effect transistor having a control electrode connected to the respective control electrodes of said first and second transistors, a first electrode connected to an input terminal of the first stage of said counter, and a second electrode connected to a power supply terminal.
Claim 4
Dependent Claim
292 words
In combination with a multistage counter circuit in which each stage includes a plurality of metal oxide semiconductor field effect transistors and first and second clock lines coupled to said transistors so that when a clock pulse is applied to said first clock line a selected one of said transistors is rendered conductive of current and when a clock pulse is applied to said second clock line a different one of said transistors is rendered conductive of current, a reset unit for resetting the stages of said circuit by the application of a selected potential level to said first and second clock lines, respectively, said unit comprising: first, second and third metal oxide semiconductor field effect transistors, each having a first electrode, a second electrode and a control electrode; the respective control electrodes of said first, second and third transistors being connected together; the first electrode of said first transistor being connected to said first clock line; the first electrode of said second transistor being connected to said second clock line; the first electrode of said third transistor being connected to an input terminal of the first stage of said circuit; a source of potential having a first terminal connected to the respective second electrodes of said first and second transistors and having a second terminal connected to the second electrode of said third transistor; and means for applying a reset pulse between the interconnected control electrodes of said first, second and third transistors and said second terminal to render said first, second and third transistors conductive of current and thereby essentially apply the potential at said first terminal to said first and second clock lines and to essentially apply the potential at said second terminal to said first stage input terminal.
Claim 5
Dependent Claim
292 words
In combination with a multistage counter circuit in which each stage includes a plurality of metal oxide semiconductor field effect transistors and first and second clock lines coupled to said transistors so that when a clock pulse is applied to said first clock line a selected one of said transistors is rendered conductive of current and when a clock pulse is applied to said second clock line a different one of said transistors is rendered conductive of current, a reset unit for resetting the stages of said circuit by the application of a selected potential level to said first and second clock lines, respectively, said unit comprising: first, second and third metal oxide semiconductor field effect transistors, each having a first electrode, a second electrode and a control electrode; the respective control electrodes of said first, second and third transistors being connected together; the first electrode of said first transistor being connected to said first clock line; the first electrode of said second transistor being connected to said second clock line; the first electrode of said third transistor being connected to an input terminal of the first stage of said circuit; a source of potential having a first terminal connected to the respective second electrodes of said first and second transistors and having a second terminal connected to the second electrode of said third transistor; and means for applying a reset pulse between the interconnected control electrodes of said first, second and third transistors and said second terminal to render said first, second and third transistors conductive of current and thereby essentially apply the potential at said first terminal to said first and second clock lines and to essentially apply the potential at said second terminal to said first stage input terminal.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1974-05-31 | 1974-11-30 | 1975-06-01 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1978-05-31 | 1978-11-30 | 1979-06-01 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1982-05-31 | 1982-11-30 | 1983-06-01 | $7700.00 | Window Closed / Lapsed |