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US3582634A
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Electrical circuit for multiplying serial binary numbers by a parallel number
Assignee: Stromberg Carlson Corp
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Filing: 1968-10-15
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Granted: 1971-06-01
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Expires: 1988-10-15
Abstract
Abstract A binary number represented by time spaced electrical pulses and intervals is multiplied by a binary multiplier represented by electrical conditions at plural spaced-apart terminals. The multiplicand is multiplied sequentially by the successive digits of the multiplier to produce partial products. The partial products are applied to binary adders and cumulatively added to produce a final product. The multiplications are done by selectively inhibiting and partially enabling gates at the inputs to the adders in accordance with the digits of the multiplier. The multiplicand signals are applied through a shift register to the gates in sequence. The adders are arranged for serial addition and in cascade.
Inventors
- 👤 William F Bartlett
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-28 13:14
CPC Classifications
G; G06; G06F; G06F7/00; G06F7/38; G06F7/48; G06F7/52; G06F7/523; G06F7/527; G06F7/5277
Claims Analysis
Total Claims: 2
Claim 1
Independent Claim
183 words
A multiplier circuit for multiplying binary numbers represented by series of time spaced electrical pulses and intervals by a binary multiplier representable by simultaneous electrical conditions at plural spaced-apart terminals comprising: a. a shift register having stages equal in number to at least one less than the number of digits to be provided for in the multiplier, b. binary adders equal in number to at least one less than the digits to be provided for in the multiplier, said adders being arranged for serial multiplication and being connected in cascade, c. gate means connecting the input and the outputs of said register to respective inputs of said adders, the input and the first output being connected to respective inputs of the first of said adders, the remaining outputs being connected respectively to inputs of the remaining respective ones of said adders, d. means for applying signals representing the multiplier respectively to said gate means for selectively inhibiting and partially enabling them in accordance with the respective digits of the multiplier, and e. means for applying the multiplicand to the input of said register.
Claim 2
Dependent Claim
183 words
A multiplier circuit for multiplying binary numbers represented by series of time spaced electrical pulses and intervals by a binary multiplier representable by simultaneous electrical conditions at plural spaced-apart terminals comprising: a. a shift register having stages equal in number to at least one less than the number of digits to be provided for in the multiplier, b. binary adders equal in number to at least one less than the digits to be provided for in the multiplier, said adders being arranged for serial multiplication and being connected in cascade, c. gate means connecting the input and the outputs of said register to respective inputs of said adders, the input and the first output being connected to respective inputs of the first of said adders, the remaining outputs being connected respectively to inputs of the remaining respective ones of said adders, d. means for applying signals representing the multiplier respectively to said gate means for selectively inhibiting and partially enabling them in accordance with the respective digits of the multiplier, and e. means for applying the multiplicand to the input of said register.
References Cited (Backward Citations)
No citation records indexed.
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1974-05-31 | 1974-11-30 | 1975-06-01 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1978-05-31 | 1978-11-30 | 1979-06-01 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1982-05-31 | 1982-11-30 | 1983-06-01 | $7700.00 | Window Closed / Lapsed |