Patent US3582633A successfully refreshed from Google Patents.
US3582633A
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Method and apparatus for fault detection in a logic circuit
Assignee: Lockheed Martin Corp
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Filing: 1968-02-20
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Granted: 1971-06-01
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Expires: 1988-02-20
Abstract
Abstract Performs an evaluation of a logic circuit by establishing a type of shift register having a sequence of shifting determined by the logic signals present at outputs of the circuit being evaluated. If the register is preset to a certain number and shifted at the consistent control of the outputs of a properly functioning circuit, the number remaining in the register at the end of the operating cycle is always the same, whatever that number may be. Inconsistent control of the shifting caused by the different logic output signals of a malfunctioning circuit produces a different number remaining in the register, indicating that the circuit has not functioned properly.
Inventors
- 👤 Robert E Webb
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-23 15:38
CPC Classifications
G; G06; G06F; G06F11/00; G06F11/22; G06F11/26; G06F11/273; G06F11/277; G06F7/00; G06F7/02
Claims Analysis
Total Claims: 12
Claim 1
Independent Claim
132 words
The method of evaluating the performance of an apparatus, comprising the steps of: operating the apparatus according to a predetermined mode; establishing a system of logic which is selectively shiftable along a determinable sequence; shifting the system of logic along said determinable sequence of logic concurrently with the operation of such apparatus, the extent along said predetermined sequence of logic of each shift being controlled by the condition of at least one output of such apparatus so that the final logical condition of the system of logic is dependent upon the number of shifts along said determinabLe sequence and upon said condition of the apparatus output; and comparing said final logical condition to the final logical condition produced by the application of the foregoing steps to an apparatus of known performance characteristics.
Claim 2
Independent Claim
132 words
The method of evaluating the performance of an apparatus, comprising the steps of: operating the apparatus according to a predetermined mode; establishing a system of logic which is selectively shiftable along a determinable sequence; shifting the system of logic along said determinable sequence of logic concurrently with the operation of such apparatus, the extent along said predetermined sequence of logic of each shift being controlled by the condition of at least one output of such apparatus so that the final logical condition of the system of logic is dependent upon the number of shifts along said determinabLe sequence and upon said condition of the apparatus output; and comparing said final logical condition to the final logical condition produced by the application of the foregoing steps to an apparatus of known performance characteristics.
Claim 3
Dependent Claim
28 words
The method of claim 10, further comprising the step of placing the sequence of logic in a predetermined logical condition prior to said step of operating the apparatus.
Claim 4
Independent Claim
183 words
The method of evaluating the performance of an apparatus, comprising the steps of: obtaining from the apparatus a number of outputs the condition of which is dependent on the functioning of the apparatus; providing a system of logic capable of being shifted along a determinable sequence; applying the conditions present on the outputs of the apparatus being evaluated as inputs to locations in the system of logic whereat the determinable sequence is dependent on the output conditions when the system of logic is shifted; presetting the system of logic to a predetermined logical condition prior to the operation of the apparatus being evaluated; operating the apparatus to be evaluated according to a predetermined mode; shifting the system of logic concurrently with said step of operating the apparatus to enable the system of logic to reach a final logical condition dependent upon the number of shifts along said sequence and upon said conditions at the time of shifting; and comparing said final logical condition to the final logical condition produced by the application of the foregoing steps to an apparatus of known performance characteristics.
Claim 5
Independent Claim
183 words
The method of evaluating the performance of an apparatus, comprising the steps of: obtaining from the apparatus a number of outputs the condition of which is dependent on the functioning of the apparatus; providing a system of logic capable of being shifted along a determinable sequence; applying the conditions present on the outputs of the apparatus being evaluated as inputs to locations in the system of logic whereat the determinable sequence is dependent on the output conditions when the system of logic is shifted; presetting the system of logic to a predetermined logical condition prior to the operation of the apparatus being evaluated; operating the apparatus to be evaluated according to a predetermined mode; shifting the system of logic concurrently with said step of operating the apparatus to enable the system of logic to reach a final logical condition dependent upon the number of shifts along said sequence and upon said conditions at the time of shifting; and comparing said final logical condition to the final logical condition produced by the application of the foregoing steps to an apparatus of known performance characteristics.
Claim 6
Dependent Claim
132 words
Apparatus for evaluating the performance of a logic device, comprising: a plurality of memory elements connected to form a logic register shiftable in a predictable sequence of logical states; said logic register having a shift pulse input and being responsive to a shift pulse applied thereto to undergo a shift of said memory elements to the next logic state in said predictable sequence of logic states; said logic register including logic control means connected to selectively control the nature of said predictable sequence of logic states in response to at least one output signal applied to said logic control means from the device being tested; and said logic control means being connected in said logic register to control the extent of said shift in response to the signal applied to said input.
Claim 7
Dependent Claim
132 words
Apparatus for evaluating the performance of a logic device, comprising: a plurality of memory elements connected to form a logic register shiftable in a predictable sequence of logical states; said logic register having a shift pulse input and being responsive to a shift pulse applied thereto to undergo a shift of said memory elements to the next logic state in said predictable sequence of logic states; said logic register including logic control means connected to selectively control the nature of said predictable sequence of logic states in response to at least one output signal applied to said logic control means from the device being tested; and said logic control means being connected in said logic register to control the extent of said shift in response to the signal applied to said input.
Claim 8
Dependent Claim
55 words
Apparatus as in claim 4, further comprising feedback means connected in said register between the output of at least one of said memory elements and the input of another of said memory elements so that the logic state shifted out of said another element is fed back to provide an input to said one element.
Claim 9
Dependent Claim
348 words
Apparatus for evaluating the performance of a logic circuit, comprising: a plurality of multiple state elements each having a signal input and a signal output, said elements being connected to form a register which is shiftable in a predictable sequence of logic states; said register having a shift pulse input circuit responsive to a shift pulse applied thereto to cause the logical condition of the register to be shifted in said predictable sequence along the register in a direction from a first one of said elements to a final one of said elements so that the logical state of each of said elements excepting said final element can be shifted out of the element toward the next element in the direction of shift; feedback circuit means extending from the signal output of at least said final element to the signal input of said first element to enable the logic state present in said final element to be shifted to said first element; a plurality of logic control gates each having a first input, a second input, and an output; the signal outputs of at least some of said elements excepting said final element being supplied to said first inputs of corresponding ones of said logic control gates and the output of each of said corresPonding logic control gates being supplied to the signal input of the next one of said elements in said register; and said second inputs of said logic control gates being connectable to receive outputs from a logic circuit to be evaluated; each of said logic control gates being operable upon receipt of a shift pulse by said register to present the next logic state in said predictable sequence to the signal input of the corresponding next one of said elements if a predetermined arrangement of signals is present at the first and second inputs to said gate and to present to such signal input a logic state in said predictable sequence other than said next state if said predetermined arrangement of signals is not present at the first and second inputs to said gates.
Claim 10
Dependent Claim
348 words
Apparatus for evaluating the performance of a logic circuit, comprising: a plurality of multiple state elements each having a signal input and a signal output, said elements being connected to form a register which is shiftable in a predictable sequence of logic states; said register having a shift pulse input circuit responsive to a shift pulse applied thereto to cause the logical condition of the register to be shifted in said predictable sequence along the register in a direction from a first one of said elements to a final one of said elements so that the logical state of each of said elements excepting said final element can be shifted out of the element toward the next element in the direction of shift; feedback circuit means extending from the signal output of at least said final element to the signal input of said first element to enable the logic state present in said final element to be shifted to said first element; a plurality of logic control gates each having a first input, a second input, and an output; the signal outputs of at least some of said elements excepting said final element being supplied to said first inputs of corresponding ones of said logic control gates and the output of each of said corresPonding logic control gates being supplied to the signal input of the next one of said elements in said register; and said second inputs of said logic control gates being connectable to receive outputs from a logic circuit to be evaluated; each of said logic control gates being operable upon receipt of a shift pulse by said register to present the next logic state in said predictable sequence to the signal input of the corresponding next one of said elements if a predetermined arrangement of signals is present at the first and second inputs to said gate and to present to such signal input a logic state in said predictable sequence other than said next state if said predetermined arrangement of signals is not present at the first and second inputs to said gates.
Claim 11
Dependent Claim
96 words
Apparatus as in claim 6, wherein: said feedback circuit means includes a feedback control gate having a first input connected to receive logic state signals shifted out of said final element in the register and a second input connected to receive logic state signals shifted out of another of said elements; said feedback control gate having an output connected to supply a certain logic state signal to the signal input of said first element if and only if a predetermined arrangement of signals is present at said first and second inputs of said feedback control gate.
Claim 12
Dependent Claim
60 words
Apparatus as in claim 6, wherein each of said logic control gates comprises an exclusive OR gate of the type which produces a certain logical output signal if an input signal is present at either of said inputs thereof and which does not produce said certain logical output signal if input signals occur simultaneously at both of said inputs thereof.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1974-05-31 | 1974-11-30 | 1975-06-01 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1978-05-31 | 1978-11-30 | 1979-06-01 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1982-05-31 | 1982-11-30 | 1983-06-01 | $7700.00 | Window Closed / Lapsed |