Automatic checkout apparatus

Claim 2

Apparatus for operationally testing a program controlled unit of a data processing system comprising; memory means for storing sets of command signals to be transmitted to the unit under test, means for reading said sets of command signals from said memory means and for transmitting them to said unit in a set by set fashion for enabling the desired portions of said unit in the desired order, reader control means for reading information for running a test from an information input means and for distributing said information to the proper portions of the apparatus, means for initiating a running of the test after said reader control means has finished distributing the information for running the test and for executing an instruction after said reading and transmitting means has transmitted all the sets of command signals to said unit under test, output means for storing and transmitting at least one data word to a portion of said unit at a selectable time during the running of a test, and input means for receiving and storing a data word from said unit under test and for comparing said input data word with an expected value, said reading and transmitting means including, means for sequentially reading the sets of command signals from said memory means, register means for storing the last set of command signals read from said memory means, and means for halting the reading from said memory means at a selected set for a selected amount of time.

Claim 3

Apparatus for operationally testing a program controlled unit of a data processing system comprising; memory means for storing sets of command signals to be transmitted to the unit under test, means for reading said sets of command signals from said memory means and for transmitting them to said unit in a set by set fashion for enabling the desired portions of said unit in the desired order, readeR control means for reading information for running a test from an information input means and for distributing said information to the proper portions of the apparatus, means for initiating a running of the test after said reader control means has finished distributing the information for running the test and for executing an instruction after said reading and transmitting means has transmitted all the sets of command signals to said unit under test, output means for storing and transmitting at least one data word to a portion of said unit at a selectable time during the running of a test, and input means for receiving and storing a data word from said unit under test and for comparing said input data word with an expected value, said output means including, register means for storing at least one data word for transmission to the unit under test, plural output path driver means having outputs connectable to selected portions of said unit, output select means for selecting a particular output path of said plural output path drivers, and timing means for causing at least one data word to be transmitted to the portion of the unit under test selected by said output select means at a selectable time after the beginning of the running of the test.

Claim 4

Apparatus for operationally testing a program controlled unit of a data processing system comprising; memory means for storing sets of command signals to be transmitted to the unit under test, means for reading said sets of command signals from said memory means and for transmitting them to said unit in a set by set fashion for enabling the desired portions of said unit in the desired order, readeR control means for reading information for running a test from an information input means and for distributing said information to the proper portions of the apparatus, means for initiating a running of the test after said reader control means has finished distributing the information for running the test and for executing an instruction after said reading and transmitting means has transmitted all the sets of command signals to said unit under test, output means for storing and transmitting at least one data word to a portion of said unit at a selectable time during the running of a test, and input means for receiving and storing a data word from said unit under test and for comparing said input data word with an expected value, said output means including, register means for storing at least one data word for transmission to the unit under test, plural output path driver means having outputs connectable to selected portions of said unit, output select means for selecting a particular output path of said plural output path drivers, and timing means for causing at least one data word to be transmitted to the portion of the unit under test selected by said output select means at a selectable time after the beginning of the running of the test.

Claim 5

Apparatus for operationally testing a program controlled unit of a data processing system comprising; memory means for storing sets of command signals to be transmitted to the unit under test, means for reading said sets of command signals from said memory means and for transmitting them to said unit in a set by set fashion for enabling the desired portions of said unit in the desired order, reader control means for reading information for running a test from an information input means and for distributing said information to the proper portions of the apparatus, means for initiating a running of the test after said reader control means has finished distributing the information for running the test and for executing an instruction after said reading and transmitting means has transmitted all the sets of command signals to said unit under test, output means for storing and transmitting at least one data word to a portion of said unit at a selectable time during the running of a test, and input means for receiving and storing a data word from said unit under test and for comparing said input data word with an expected value, said input means including, register means for storing the data word received from said unit under test, multi-input path receiver means for receiving said data word from a selectable portion of said unit and for inserting said data word into said register means, input select means for selecting one of said input paths, and input timing means for enabling said input register to receive said data word from said unit under test at a selectable time after the beginning of the running of said test.

Claim 6

Apparatus for operationally testing a program controlled unit of a data processing system comprising; memory means for storing sets of command signals to be transmitted to the unit under test, means for reading said sets of command signals from said memory means and for transmitting them to said unit in a set by set fashion for enabling the desired portions of said unit in the desired order, reader control means for reading information for running a test from an information input means and for distributing said information to the proper portions of the apparatus, means for initiating a running of the test after said reader control means has finished distributing the information for running the test and for executing an instruction after said reading and transmitting means has transmitted all the sets of command signals to said unit under test, output means for storing and transmitting at least one data word to a portion of said unit at a selectable time during the running of a test, and input means for receiving and storing a data word from said unit under test and for comparing said input data word with an expected value, said input means including, register means for storing the data word received from said unit under test, multi-input path receiver means for receiving said data word from a selectable portion of said unit and for inserting said data word into said register means, input select means for selecting one of said input paths, and input timing means for enabling said input register to receive said data word from said unit under test at a selectable time after the beginning of the running of said test.

Claim 7

Apparatus for operationally testing a program controlled unit of a data processing system comprising; memory means for storing sets of command signals to be transmitted to the unit under test, means for reading said sets of command signals from said memory means and for transmitting them to said unit in a set by set fashion for enabling the desired portions of said unit in the desired order, reader control means for reading information for running a test from an information input means and for distributing said information to the proper portions of the apparatus, means for initiating a running of the test after said reader control means has finished distributing the formation for running the test and for executing an instruction after said reading and transmitting means has transmitted all the sets of command signals to said unit under test, output means for storing and transmitting at least one data word to a portion of said unit at a selectable time during the running of a test, and input mEans for receiving and storing a data word from said unit under test and for comparing said input data word with an expected value, said reader control means including, input buffer register means for receiving the information for running a test from said information input test means in the form of a series of groups of multibit characters, the first character in any group being a tape command which contains an operation code specifying the significance of the information contained in the group, and the second character of any group being a character count which indicates the number of characters in the group, tape command register means for storing the operation code of the tape command received from said input buffer register means, character counter means for receiving and down counting the character count received from the input buffer register means and decoding means for decoding the contents of said tape command register means and said character counter means for distributing the information in the group of characters in accordance with the operation code of the tape command.

Claim 8

Apparatus for operationally testing a program controlled unit of a data processing system comprising; memory means for storing sets of command signals to be transmitted to the unit under test, means for reading said sets of command signals from said memory means and for transmitting them to said unit in a set by set fashion for enabling the desired portions of said unit in the desired order, reader control means for reading information for running a test from an information input means and for distributing said information to the proper portions of the apparatus, means for initiating a running of the test after said reader control means has finished distributing the formation for running the test and for executing an instruction after said reading and transmitting means has transmitted all the sets of command signals to said unit under test, output means for storing and transmitting at least one data word to a portion of said unit at a selectable time during the running of a test, and input mEans for receiving and storing a data word from said unit under test and for comparing said input data word with an expected value, said reader control means including, input buffer register means for receiving the information for running a test from said information input test means in the form of a series of groups of multibit characters, the first character in any group being a tape command which contains an operation code specifying the significance of the information contained in the group, and the second character of any group being a character count which indicates the number of characters in the group, tape command register means for storing the operation code of the tape command received from said input buffer register means, character counter means for receiving and down counting the character count received from the input buffer register means and decoding means for decoding the contents of said tape command register means and said character counter means for distributing the information in the group of characters in accordance with the operation code of the tape command.

Claim 9

The apparatus of claim 4 wherein said reader control means further includes, means for determining whether the series of groups of characters being received by the input buffer register means is for the next test to run by said apparatus.

Claim 10

Apparatus for operationally testing a program controlled unit of a data processing system comprising; memory means for storing sets of command signals to be transmitted to the unit under test, means for reading said sets of command signals from said memory means and for transmitting them to said unit in a set by set fashion for enabling the desired portions of said unit in the desired order, reader control means for reading information for running a test from an information input means and for distributing said information to the proper portions of the apparatus, means for initiating a running of the test after said reader control means has finished distributing the information for running the test and for executing an instruction after said reading and transmitting means has transmitted all the sets of command signals to said unit under test, output means for storing and transmitting at least one data word to a portion of said unit at a selectable time during the running of a test, and input means for receiving and storing a data word from said unit under test and for comparing said input data word with an expected value, said initiating and executing means including, register means for storing the instruction to be executed after all the sets of command signals have been transmitted, repeat counter means for indicating the number of times a test is to be repeated if repetition of the test is specified by the instructions in said register means, and logic means for decrementing the contents of said repeat counter means after each repetition of a test.

Claim 11

Apparatus for operationally testing a program controlled unit of a data processing system comprising; memory means for storing sets of command signals to be transmitted to the unit under test, means for reading said sets of command signals from said memory means and for transmitting them to said unit in a set by set fashion for enabling the desired portions of said unit in the desired order, reader control means for reading information for running a test from an information input means and for distributing said information to the proper portions of the apparatus, means for initiating a running of the test after said reader control means has finished distributing the information for running the test and for executing an instruction after said reading and transmitting means has transmitted all the sets of command signals to said unit under test, output means for storing and transmitting at least one data word to a portion of said unit at a selectable time during the running of a test, and input means for receiving and storing a data word from said unit under test and for comparing said input data word with an expected value, said initiating and executing means including, register means for storing the instruction to be executed after all the sets of command signals have been transmitted, repeat counter means for indicating the number of times a test is to be repeated if repetition of the test is specified by the instructions in said register means, and logic means for decrementing the contents of said repeat counter means after each repetition of a test.

Claim 12

Apparatus for performing a plurality of operational tests on a component of a data processing system, said component being operated at a first clock rate, comprising: means for storing sets of enable signals and for transmitting them in a set by set fashion to said component at the first clock rate for enabling the various portions of said component in a desired order to perform an operation on data with said component, output means for storing a data word and for transmitting said data word to said component under test at a selectable time after the beginning of the transmission of said sets of enable signals to said component, input means for receiving a data word from said component under test and for comparing said input data word with an expected value, means for reading information to run a test from an information input means and for distributing said information to the proper portions of said apparatus said reading and distributing means operating at a second clock rate, and means operating at said first clock rate for initiating the transmitting of the sets of enable signals to said component after said reading means has finished distributing the information to run the test and operating at the second clock rate to execute an instruction after said storing and transmitting means has finished transmitting said sets of enable signals to said component.

Claim 13

Apparatus for performing a plurality of operational tests on a component of a data processing system, said component being operated at a first clock rate, comprising: means for storing sets of enable signals and for transmitting them in a set by set fashion to said component at the first clock rate for enabling the various portions of said component in a desired order to perform an operation on data with said component, output means for storing a data word and for transmitting said data word to said component under test at a selectable time after the beginning of the transmission of said sets of enable signals to said component, input means for receiving a data word from said component under test and for comparing said input data word with an expected value, means for reading information to run a test from an information input means and for distributing said information to the proper portions of said apparatus said reading and distributing means operating at a second clock rate, and means operating at said first clock rate for initiating the transmitting of the sets of enable signals to said component after said reading means has finished distributing the information to run the test and operating at the second clock rate to execute an instruction after said storing and transmitting means has finished transmitting said sets of enable signals to said component.

Claim 14

The apparatus of claim 7 wherein said storing and transmitting means includes: a memory for storing said sets of enable signals, register means, memory addressing means for sequentially reading said sets of enable signals out of said memory into said register means at said first clock rate, means for halting for a selectable number of first clock times the reading from said memory after a selectable of one of said sets of enable signals is read into said register means.

Claim 15

The apparatus of claim 7 wherein said reading and distributing means includes: input buffer register means for receiving the information for running a test from said information input means in the form of a series of groups of multibit characters, the first character in any group being a tape command which contains an operation code telling the significance of the information contained in the group, and the second character of any group being a character count which indicates the number of characters in the group, tape command register means for storing the operation code of the tape command received from said input buffer register means, character counter means for receiving and down counting the character count received from the input buffer register means, and decoding means for decoding the contents of said tape command register means and said character counter means for distributing the information in the group of characters in accordance with the operation code of the tape command.