Isolation circuit for gating devices

Claim 2

A buffer circuit between an output terminal and a logic gating circuit comprising, a first switching device having a control electrode connected to said logic gating circuit, an output electrode connected to said output terminal, and another electrode connectable to a clock signal, said logic gating circuit providing drive voltages to said control electrode for rendering said first switching device conductive and nonconductive as a function of the voltage levels of said drive voltages, capacitor means connected between said output electrode and said control electrode for feeding back voltage on the output terminal to the control electrode during one interval of said clock signal when the first switching device is conductive for increasing the drive voltage of said first switching device until the voltage on the output terminal is greater than the voltage on the output terminal at the beginning of said one interval, a second switching device connected in parallel with said first switching device for connecting the output terminal to a voltage level representing a false logic state during the interval prior to said one interval of said clock signal.

Claim 3

A buffer circuit between an output terminal and a logic gating circuit comprising, a first switching device connected between a clock signal and an output electrode and having a control electrode connected to said logic gating circuit, said logic gating circuit providing drive voltages to said control electrode for rendering said first switching device conductive and nonconductive as a function of the voltage levels of said drive voltages, capacitor means connected between said output electrode and said control electrode for feeding back voltage on the output terminal to the control electrode during one interval of said clock signal when the first switching device is conductive for increasing the drive voltage of said first switching device until the voltage on the output terminal attributed to said clock signal is greater than the voltage on the output terminal at the beginning of said one interval, a second switching device connected in parallel with the first switching device to connect the output terminal to a voltage representing a false logic state during an interval prior to said one interval for preventing a drive voltage level which would render said first switching device nonconductive during said one interval from being coupled to the output terminal across said capacitor means.

Claim 4

A buffer circuit between an output terminal and a logic gating circuit comprising, a first switching device connected between a clock signal and an output electrode and having a control electrode connected to said logic gating circuit, said logic gating circuit providing drive voltages to said control electrode for rendering said first switching device conductive and nonconductive as a function of the voltage levels of said drive voltages, capacitor means connected between said output electrode and said control electrode for feeding back voltage on the output terminal to the control electrode during one interval of said clock signal when the first switching device is conductive for increasing the drive voltage of said first switching device until the voltage on the output terminal attributed to said clock signal is greater than the voltage on the output terminal at the beginning of said one interval, a second switching device connected in parallel with the first switching device to connect the output terminal to a voltage representing a false logic state during an interval prior to said one interval for preventing a drive voltage level which would render said first switching device nonconductive during said one interval from being coupled to the output terminal across said capacitor means.

Claim 5

A field effect transistor isolation circuit between an output terminal having load capacitance associated therewith and a logic gating circuit which provides drive voltages having voltage levels representing logic states to said isolation field effect transistor circuit during certain recurring intervals, said circuit comprising, a first field effect transistor connected between a phase recurring clock signal and said output terminal and having a gate electrode connected to said logic gating circuit, said first phase recurring clock signal having a voltage level representing a lOgic false state when the logic gating circuit is providing a drive voltage to said gate electrode, and a voltage level representing a logic true state during the interval after a drive voltage is provided to said gate electrode by said logic gating circuit, feedback capacitor means connected between the output terminal and said gate electrode for feeding back voltage on the output terminal to the gate electrode during the interval that the voltage level of the first phase recurring clock signal represents a logic true state and when the drive voltage on the gate electrode renders said first field effect transistor conductive, said feedback voltage increasing the drive voltage on the gate electrode for enhancing the conduction of the field effect transistor until the voltage on the output terminal is increased from the voltage initially on the output terminal is increased from the voltage initially on the output terminal at the beginning of the feedback interval, said load capacitance at the output terminal being large relative to said capacitor means for maintaining said output terminal at a voltage level representing a false logic state during the interval when said logic gating circuit provides a change from a previous interval in drive voltage from a voltage level representing a true logic state to a voltage level representing a false logic state and for enabling said capacitor means to charge to the difference between the drive voltage provided by said logic gating circuit and the voltage level on the output terminal during an interval when the drive voltage has a level representing a true logic level whereby the voltage being fed back across said capacitor means from the output terminal causes an increase in the voltage on said gate electrode in excess of the voltage on said capacitor means at the beginning of said interval.

Claim 6

A field effect transistor isolation circuit between an output terminal having load capacitance associated therewith and a logic gating circuit which provides drive voltages having voltage levels representing logic states to said isolation field effect transistor circuit during certain recurring intervals, said circuit comprising, a first field effect transistor connected between a phase recurring clock signal and said output terminal and having a gate electrode connected to said logic gating circuit, said first phase recurring clock signal having a voltage level representing a lOgic false state when the logic gating circuit is providing a drive voltage to said gate electrode, and a voltage level representing a logic true state during the interval after a drive voltage is provided to said gate electrode by said logic gating circuit, feedback capacitor means connected between the output terminal and said gate electrode for feeding back voltage on the output terminal to the gate electrode during the interval that the voltage level of the first phase recurring clock signal represents a logic true state and when the drive voltage on the gate electrode renders said first field effect transistor conductive, said feedback voltage increasing the drive voltage on the gate electrode for enhancing the conduction of the field effect transistor until the voltage on the output terminal is increased from the voltage initially on the output terminal is increased from the voltage initially on the output terminal at the beginning of the feedback interval, said load capacitance at the output terminal being large relative to said capacitor means for maintaining said output terminal at a voltage level representing a false logic state during the interval when said logic gating circuit provides a change from a previous interval in drive voltage from a voltage level representing a true logic state to a voltage level representing a false logic state and for enabling said capacitor means to charge to the difference between the drive voltage provided by said logic gating circuit and the voltage level on the output terminal during an interval when the drive voltage has a level representing a true logic level whereby the voltage being fed back across said capacitor means from the output terminal causes an increase in the voltage on said gate electrode in excess of the voltage on said capacitor means at the beginning of said interval.

Claim 7

The isolation circuit recited in claim 3 wherein a second field effect transistor is connected in electrical parallel with said first field effect transistor.

Claim 8

An isolation circuit between an output terminal having load capacitance and a logic gating circuit, said circuit comprising, a first field effect transistor connected between a phase recurring clock signal and said output terminal and having a gate electrode, said logic gating circuit providing drive voltages to said gate electrode for controlling the conduction of said first field effect transistor, feedback capacitor means connected between said output terminal and said gate electrode for feeding back a voltage level on said output terminal when said first field effect transistor is rendered conductive by a drive voltage, the feedback voltage having an amplitude approximately equal to the voltage level of said phase recurring clock signal, said feedback capacitor means being small relative to said load capacitance for maintaining said output terminal at a required voltage level when the voltage level at the gate electrode of said first field effect transistor is changed from one voltage level to a different voltage level by a drive voltage from said logic gating circuit.

Claim 9

An isolation circuit between an output terminal having load capacitance and a logic gating circuit, said circuit comprising, a first field effect transistor connected between a phase recurring clock signal and said output terminal and having a gate electrode, said logic gating circuit providing drive voltages to said gate electrode for controlling the conduction of said first field effect transistor, feedback capacitor means connected between said output terminal and said gate electrode for feeding back a voltage level on said output terminal when said first field effect transistor is rendered conductive by a drive voltage, the feedback voltage having an amplitude approximately equal to the voltage level of said phase recurring clock signal, said feedback capacitor means being small relative to said load capacitance for maintaining said output terminal at a required voltage level when the voltage level at the gate electrode of said first field effect transistor is changed from one voltage level to a different voltage level by a drive voltage from said logic gating circuit.

Claim 10

The isolation circuit recited in claim 5 wherein said logic gating circuit provides a first drive voltage level for rendering said first field effect transistor conductive during a first phase of said phase recurring clock signal, said clock signal having a second voltage level during said first phase, said output terminal being set to said second voltage level for enabling said feedback capacitor means to charge to the difference between said first and second voltage levels, and during a second phase of said phase recurring clock signal if the drive voltage changes to a second voltage level for rendering said first field effect transistor nonconductive, the size of the load capacitance relative to the feedback capacitor means enabling said output terminal to remain at the second voltage level at least for said second phase.

Claim 11

The isolation circuit recited in claim 6 wherein said firsT drive voltage level represents a true logic state, said second voltage level represents a false logic state, said phase recurring clock signal having a voltage level representing a true logic state during said second phase whereby when said first field effect transistor is rendered conductive by a drive voltage representing a true logic state at the beginning of said second phase, said voltage level at the output terminal being initially reduced by a threshold voltage drop across said first field effect transistor, the feedback of the initial voltage level through said feedback capacitor means to said gate electrode enhancing the conduction by said first field effect transistor for overcoming said threshold drop whereby the output terminal is driven to the voltage level of said phase recurring clock signal during said second phase.