Patent US3579223A successfully refreshed from Google Patents.
US3579223A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Transistorized monitoring circuit
Assignee: Individual
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Filing: 1968-06-25
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Granted: 1971-05-18
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Expires: 1988-06-25
Abstract
Abstract The invention consists of modifications and improvements to the monitoring circuit of U.S. Pat. No. 3,293,630. These changes increase the sensitivity and accuracy of the monitoring circuit by an improved interconnection with the monitored circuit, provide an adjustment to compensate for manufacturing tolerances in components, provide an adjustment for matching the monitoring circuit to the monitored circuit, eliminate problems with alternating current waveshape in the monitored circuit, eliminate false indications by effective use of time delay circuits and furnish more usable monitoring information by including a gating circuit.
Inventors
- 👤 Arthur B Mckaig
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-29 19:28
CPC Classifications
G; G08; G08G; G08G1/00; G08G1/097
Claims Analysis
Total Claims: 5
Claim 1
Independent Claim
213 words
A circuit for use with a basic electrical monitoring circuit for producing an indication whenever the magnitude of a monitored electrical signal deviates beyond at least one predetermined limit, said circuit comprising a source of direct current potential, first and second transistors having their emitters connected in common to the positive side of said source through a first resistor and having the base of said first traNsistor and the collector of said second transistor connected in common to the negative side of said source through a second resistor, an indicator connected between the collector of said first transistor and the negative side of said source, means including said source for normally biasing said second transistor to a predetermined conductive level such that its emitter to collector potential maintains said first transistor nonconductive, a third resistor connected across a direct current signal proportional in magnitude to the magnitude of said monitored electrical signal, said third resistor also connected between the base of said second transistor and said normal biasing means, said direct current signal thus supplementing the potential applied to said second transistor emitter base circuit by said biasing means, whereby, when said direct current signal diminishes to a predetermined magnitude, the emitter-collector potential of said second transistor causes conduction by said first transistor.
Claim 2
Dependent Claim
213 words
A circuit for use with a basic electrical monitoring circuit for producing an indication whenever the magnitude of a monitored electrical signal deviates beyond at least one predetermined limit, said circuit comprising a source of direct current potential, first and second transistors having their emitters connected in common to the positive side of said source through a first resistor and having the base of said first traNsistor and the collector of said second transistor connected in common to the negative side of said source through a second resistor, an indicator connected between the collector of said first transistor and the negative side of said source, means including said source for normally biasing said second transistor to a predetermined conductive level such that its emitter to collector potential maintains said first transistor nonconductive, a third resistor connected across a direct current signal proportional in magnitude to the magnitude of said monitored electrical signal, said third resistor also connected between the base of said second transistor and said normal biasing means, said direct current signal thus supplementing the potential applied to said second transistor emitter base circuit by said biasing means, whereby, when said direct current signal diminishes to a predetermined magnitude, the emitter-collector potential of said second transistor causes conduction by said first transistor.
Claim 3
Dependent Claim
78 words
The circuit as defined in claim 1 and including a third transistor having its emitter connected to the positive side of said potential source, with the base of said third transistor connected to the collector of said first transistor by means of a fourth resistor, and with the collector of said third transistor connected through an indicator to the negative side of said potential source, whereby, said third transistor thus conducts out of phase with said first transistor.
Claim 4
Dependent Claim
124 words
The circuit as defined in claim 1 and including a fourth transistor controlling the output indication signal from the collector of said first transistor, said fourth transistor having its emitter connected to the collector of said first transistor and the collector of said fourth transistor serving as output terminal, with the emitter and base of said fourth transistor being connected to an external biasing voltage, a fifth resistor connected between said collector of said fourth transistor and the negative side of said potential source, the application of said biasing voltage causing said fourth transistor to conduct and thus provide said output indication signal, or contrariwise, the absence of said biasing voltage preventing said fourth transistor from conducting and thus blocking said output indication signal.
Claim 5
Dependent Claim
184 words
The circuit as defined in claim 3 and including means for biasing said fourth transistor, said means for biasing comprising at least a sixth, seventh and eighth resistors connected in series across a control signal potential source with the junction of said sixth and seventh resistors connected to the emitter of said fourth transistor and the negative of said control signal potential connected to the base of said fourth transistor, a time-delay capacitor connected to the junction of said seventh and eighth resistors and to the negative of said control signal potential, a ninth resistor connected across said control signal potential, and a fifth transistor with emitter connected to the junction of said seventh and eighth resistors and with base connected to positive and collector connected to negative of said control signal potential, whereby conduction of said fourth transistor is delayed by charging time for said time-delay capacitor after said control signal potential is applied, and conduction of said fourth transistor ceases immediately after removal of said control signal potential due to immediate discharge of said time-delay capacitor by conduction of said fifth transistor.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1974-05-17 | 1974-11-16 | 1975-05-18 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1978-05-17 | 1978-11-16 | 1979-05-18 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1982-05-17 | 1982-11-16 | 1983-05-18 | $7700.00 | Window Closed / Lapsed |