Patent US3579128A successfully refreshed from Google Patents.
US3579128A
Expired / Lapsed
US
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Phase controller
Assignee: Individual
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Filing: 1969-02-12
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Granted: 1971-05-18
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Expires: 1989-02-12
Abstract
Abstract The subject disclosure relates to novel and improved apparatus for detecting and nulling the difference in phase between a pair of electrical operational channels. The apparatus includes a signal generator which applies a test signal to each operational channel, a phase detector coupled to the output of the channels, an analog to digital converter that converts the detected phase difference into a count in and up and down counter circuit and switching devices that in response to the output of the counter couple phase shift elements into one of the channels so as to equalize the phase between the two channels.
Inventors
- 👤 Ervin Smith
- 👤 John O Wedel
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-02 07:27
CPC Classifications
G; G01; G01R; G01R25/00; G01R25/005; H; H03; H03H; H03H7/00; H03H7/18; H03H7/185; H03H7/20; H04; H04L; H04L7/00
Claims Analysis
Total Claims: 6
Claim 1
Independent Claim
219 words
In a system for automatically controlling the phase difference between a pair of operational channels, the combination compriSing: a. means for applying a test signal into the two channels at the operating frequency thereof; b. a phase detector coupled to the output of the two channels to detect a phase difference therebetween and for generating a proportional output error signal; c. and a phase controller digital logic circuit coupled between the input of the phase detector and the output of one of the channels and responsive to the output error signal from said phase detector to adjust the phase of said one channel, thereby equalizing the phase difference between the two channels, said phase controller digital logic circuit comprising a time delay network having a plurality of fixed phase shift elements coupled between the output of the one channel and the input of the phase detector; an up-down digital counter; means coupled between the output of the phase detector and the up-down counter for producing a count in said up-down counter in response to the output error signal from said phase detector; and means responsive to the output count from the up-down counter to selectively switch the necessary number of phase shift elements in or out of the time delay network to equalize the phase between the two channels.
Claim 2
Dependent Claim
219 words
In a system for automatically controlling the phase difference between a pair of operational channels, the combination compriSing: a. means for applying a test signal into the two channels at the operating frequency thereof; b. a phase detector coupled to the output of the two channels to detect a phase difference therebetween and for generating a proportional output error signal; c. and a phase controller digital logic circuit coupled between the input of the phase detector and the output of one of the channels and responsive to the output error signal from said phase detector to adjust the phase of said one channel, thereby equalizing the phase difference between the two channels, said phase controller digital logic circuit comprising a time delay network having a plurality of fixed phase shift elements coupled between the output of the one channel and the input of the phase detector; an up-down digital counter; means coupled between the output of the phase detector and the up-down counter for producing a count in said up-down counter in response to the output error signal from said phase detector; and means responsive to the output count from the up-down counter to selectively switch the necessary number of phase shift elements in or out of the time delay network to equalize the phase between the two channels.
Claim 3
Dependent Claim
96 words
In a system substantially as described in claim 1 wherein the means for producing a count in the up-down counter includes: a. an analog-to-digital converter responsive to the output error signal from the phase detector for generating a digitized output indicative of the instantaneous voltage level of said phase detector; b. and an up clock and a down clock generator coupled between the digitized output from the converter and the input of the counter in a parallel configuration, for generating timing pulses in response to said digitized output signal for producing an up or down count.
Claim 4
Dependent Claim
98 words
In a system substantially as described in claim 1 wherein the switch means includes: a. a plurality of normally closed switches connected serially, each of said switches further connected in a shunt arrangement with an individual phase shift element; b. and a plurality of switch actuators coupled between the output of the up-down counter and each of the switches to selectively open or close a multiplicity of said switches in response to a predetermined count from said counter, whereby the necessary phase shift is included in the one channel output to equalize the phase between the two channels.
Claim 5
Dependent Claim
75 words
In a system substantially as described in claim 3, where the phase controller digital logic circuit further comprises an AND gate coupled between the plurality of switch actuators and the up-down counter for resetting the counter to a predetermined count in response to the actuation of said plurality of switch actuators, whereby a multiplicity of the phase shift elements are shunted so that approximately 190* of phase shift is taken out of the one channel.
Claim 6
Dependent Claim
131 words
In a system substantially as described in claim 4 wherein: a. The up-down counter comprises n stages having a total count of 2n-1; b. the time delay network comprises n phase shift elements having a total combined phase shift greater than 360*, said n phase shift elements having a phase shift distribution according to the formula 2N 1 ( phi )/2n where phi is the total combined phase shift and N is a positive whole number from 1 to n; c. and wherein the up and down clock generators are continuously running in sequence after an output null voltage has been achieved by the phase detector, thereby cycling the smallest increment of phase change in and out of the one channel to insure that a proper null position has been achieved.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1974-05-17 | 1974-11-16 | 1975-05-18 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1978-05-17 | 1978-11-16 | 1979-05-18 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1982-05-17 | 1982-11-16 | 1983-05-18 | $7700.00 | Window Closed / Lapsed |