Phase lock indicator for plural phase lock loops

Claim 2

In a phase comparison system having a plurality of phase tracking loops: phase lock indicating means comprising: a. a phase detector having an equal plurality of incoming signals fed to the signal waveform input thereof and having the output of each of said phase tracking loops fed sequentially to the reference input thereof in respective coincidence with said incoming signals, b. a reset integrator connected to the output of said phase detector, means for resetting said integrator to zero between each one of said incoming signals, c. a level detector connected to the output of said reset integrator, said level detector having a push-pull output, d. a plurality of flip-flops connected in parallel with each other to said push-pull output, logical gate means for triggering each of said flip-flops only at the times of their respective phase signal from said level detector, and e. an indicating lamp circuit operatively connected to an output of each of said flip-flops.

Claim 3

In a navigation receiver having means for receiving a transmitted series of radio frequency bursts differing with respect to phase, and having a plurality of phase tracking loops adapted to phase lock with respective corresponding bursts: phase lock indicating means comprising: a. an in-phase detector adapted to produce a series of pulses each directly proportional in amplitude to the degree with which each of an output from said phase tracking loops is in-phase with its corresponding burst, b. a reset integrator connected to integrate each pulse of said series of pulses, means for resetting said integrator to zero after each of said pulses, c. a level detector connected to the output of said integrator and having a predetermined threshold level for passing or not passing each of said integrated pulses, means for producing a push-pull output from said level detector, d. a plurality of R-S flip-flops equal in number to said phase tracking loops, means connected to Sc and Rc terminals of said flip-flops in parallel with each other and to said push-pull output, e. logic means connected to the clock terminal of each of said flip-flops to store the output level of said level detector only at the times said level detector output carries the signal from the corresponding phase loop, and f. an indicator lamp circuit operatively connected to an output of each flip-flop.

Claim 4

In a navigation receiver having means for receiving a transmitted series of radio frequency bursts differing with respect to phase, and having a plurality of phase tracking loops adapted to phase lock with respective corresponding bursts: phase lock indicating means comprising: a. an in-phase detector adapted to produce a series of pulses each directly proportional in amplitude to the degree with which each of an output from said phase tracking loops is in-phase with its corresponding burst, b. a reset integrator connected to integrate each pulse of said series of pulses, means for resetting said integrator to zero after each of said pulses, c. a level detector connected to the output of said integrator and having a predetermined threshold level for passing or not passing each of said integrated pulses, means for producing a push-pull output from said level detector, d. a plurality of R-S flip-flops equal in number to said phase tracking loops, means connected to Sc and Rc terminals of said flip-flops in parallel with each other and to said push-pull output, e. logic means connected to the clock terminal of each of said flip-flops to store the output level of said level detector only at the times said level detector output carries the signal from the corresponding phase loop, and f. an indicator lamp circuit operatively connected to an output of each flip-flop.

Claim 5

Apparatus in accordance with claim 2 wherein said clock signal to each flip-flop occurs late in the period of its respective transmitted burst, and wherein said indicator lamp circuits comprise means for illuminating a respective lamp to indicate a ''''not phase locked'''' condition.

Claim 6

In a phase comparison system having a plurality of phase tracking loops: phase lock indicating means comprising a single reset integrator, means for supplying said integrator with a sequence of pulses proportional in amplitude to the degree of desired phase lock condition of each of said tracking loops, means for resetting said integrator between pulses, a level detector connected to the output of said reset integrator, one bistable trigger circuit for each said phase tracking loop, said trigger circuits connected in parallel to the output of said level detector, means for controlling the state of each trigger circuit in accordance with the output of said level detector associated with the corresponding phase loop, and visual indicating means connected to an output of each said trigger circuit.

Claim 7

In a phase comparison system having a plurality of phase tracking loops: phase lock indicating means comprising a single reset integrator, means for supplying said integrator with a sequence of pulses proportional in amplitude to the degree of desired phase lock condition of each of said tracking loops, means for resetting said integrator between pulses, a level detector connected to the output of said reset integrator, one bistable trigger circuit for each said phase tracking loop, said trigger circuits connected in parallel to the output of said level detector, means for controlling the state of each trigger circuit in accordance with the output of said level detector associated with the corresponding phase loop, and visual indicating means connected to an output of each said trigger circuit.

Claim 8

Apparatus in accordance with claim 4 wherein said supply means to said reset integrator comprises an in-phase detector.

Claim 9

Apparatus in accordance with claim 4 wherein each said trigger circuit comprises an R-S type flip-flop, and said trigger circuit controlling means comprises a plurality of gate means having their outputs connected respectively To the clock terminals of said flip-flops, and gate control means for opening each of said gates only during a portion of the time that the level detector output corresponds to its respective phase loop signal.