Patent US3576682A successfully refreshed from Google Patents.
US3576682A
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Method of making complementary transistors in monolithic integrated circuit
Assignee: US Philips Corp
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Filing: 1968-02-05
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Granted: 1971-04-27
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Expires: 1988-02-05
Abstract
Abstract A METHOD IS DESCRIBED OF MAKING A MONOLITHIC 1C WITH COMPLEMENTARY TRANSISTORS WHEREIN THE P-EMITTER OF THE PNP TRANSISTOR IS FIFFUSED SIMULTANEOUSLY WITH THE P-ISOLATION WALLS, FOLLOWED BY SIMULTANEOUS DIFFUSION OF THE PBASE OF THE NPN TRANSISTOR AND THE P-COLLECTOR OF THE PNP TRANSISTOR, FOLLOWED BY SIMULTANEOUS DIFFUSION OF THE NEMITTER FOR THE NPN TRANSISTOR AND THE N-CONTACT REGIONS FOR THE NPN-COLLECTOR AND THE PNP-BASE.
Inventors
- 👤 Jean-Claude Frouin
- 👤 Michel De Brebisson
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-04 06:47
CPC Classifications
H; H10; H10D; H10D84/00; H10D84/01; H10D84/0112; H10D84/0114; H10D84/02; H10D84/03; H10D84/038; H10D84/60; H10D84/63; H10W; H10W10/00; H10W10/01; H10W10/031; H10W10/30
Claims Analysis
Total Claims: 0
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References Cited (Backward Citations)
No citation records indexed.
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1974-04-26 | 1974-10-26 | 1975-04-27 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1978-04-26 | 1978-10-26 | 1979-04-27 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1982-04-26 | 1982-10-26 | 1983-04-27 | $7700.00 | Window Closed / Lapsed |