Binary coded digital to analog converter

Claim 2

Binary coded digital to analog converter comprising: a n-bit buffer for storing a n-bit binary coded signal which is to be converted into analog signals, first generating means for generating a first two level voltage waveform representative of the value in said buffer, second generating means for generating a second two level voltage waveform representative of the binary complement of said value in the buffer, inverting means for inverting the polarity of said second waveform, summing means for summing the output signals from said first generating means and from said inverting means, thereby providing a third waveform, and filter means responsive to said third waveform for providing an analog signal corresponding to said n-bit binary coded signal.

Claim 3

Binary coded digital to analog converter comprising: a n-bit buffer for storing successively different n-bit binary coded signals which are to be converted into analog signals, first clock means generating timing pulses at a first frequency for controlling the entering of said different binary coded signals into said buffer, thus determining a period of time T during which each of said binary coded signals remains in said buffer, first generating means for generating a first two level voltage waveform representative of the binary value of the signal in the buffer during said period T, second generating means for generating a second two level voltage waveform representative of the binary complement of the value in the buffer during said same period T, inverting means for inverting the polarity of said second waveform, summing means for summing the output signals from said first generating means and from said inverting means, thereby providing a third waveform, and means for integrating said third waveform to provide an analog corresponding to said binary coded signal.

Claim 4

Binary coded digital to analog converter comprising: a n-bit buffer for storing successively different n-bit binary coded signals which are to be converted into analog signals, first clock means generating timing pulses at a first frequency for controlling the entering of said different binary coded signals into said buffer, thus determining a period of time T during which each of said binary coded signals remains in said buffer, first generating means for generating a first two level voltage waveform representative of the binary value of the signal in the buffer during said period T, second generating means for generating a second two level voltage waveform representative of the binary complement of the value in the buffer during said same period T, inverting means for inverting the polarity of said second waveform, summing means for summing the output signals from said first generating means and from said inverting means, thereby providing a third waveform, and means for integrating said third waveform to provide an analog corresponding to said binary coded signal.

Claim 5

Binary coded to analog converter comprising: n-bit buffer for storing successively different n-bit binary coded signals which are to be converted into analog signals, first clock means generating timing pulses at a first frequency for controlling the entering of said different binary coded signals into said buffer, a n-bit counter, a second clock means generating timing pulses at a second frequency for causing said counter to increase in value, said second clock frequency being at least equal to 2n times said first clock frequency, detecting means for detecting the maximum value of the counter and providing a first control pulse each time said maximum value is detected, a first digital comparator comprising at any instant the value in the counter and the value in the buffer, and providing a second control pulse when equality is detected, first latch means controlled by said first comparator output and said detecting means output for providing a first direct voltage level in response to said first control pulse and a second direct voltage level upon occurence of said second control pulse thereby providing a first two level voltage waveform, a second digital comparator comparing at any instant the value in the counter and the binary complement of the value in the buffer, and providing a third control pulse when equality is detected, second latch means controlled by said second comparator output and said detecting means output for said second voltage level in response to said first control pulses and said first voltage level in response to said third control pulse, thereby providing a second two level voltage waveform, summing means for summing said first and second two level waveforms, thereby providing a third waveform, and means for integrating said third waveform to provide an analog signal corresponding to said binary coded signal.

Claim 6

Binary coded to analog converter comprising: n-bit buffer for storing successively different n-bit binary coded signals which are to be converted into analog signals, first clock means generating timing pulses at a first frequency for controlling the entering of said different binary coded signals into said buffer, a n-bit counter, a second clock means generating timing pulses at a second frequency for causing said counter to increase in value, said second clock frequency being at least equal to 2n times said first clock frequency, detecting means for detecting the maximum value of the counter and providing a first control pulse each time said maximum value is detected, a first digital comparator comprising at any instant the value in the counter and the value in the buffer, and providing a second control pulse when equality is detected, first latch means controlled by said first comparator output and said detecting means output for providing a first direct voltage level in response to said first control pulse and a second direct voltage level upon occurence of said second control pulse thereby providing a first two level voltage waveform, a second digital comparator comparing at any instant the value in the counter and the binary complement of the value in the buffer, and providing a third control pulse when equality is detected, second latch means controlled by said second comparator output and said detecting means output for said second voltage level in response to said first control pulses and said first voltage level in response to said third control pulse, thereby providing a second two level voltage waveform, summing means for summing said first and second two level waveforms, thereby providing a third waveform, and means for integrating said third waveform to provide an analog signal corresponding to said binary coded signal.

Claim 7

Binary coded digital to analog converter according to claim 3 wherein: said first latch means comprises: a first bistable device controlled by said respective first and second control pulses so as to provide no output signal in response to said first control pulse and an output signal in response to said second control pulse, a first two position switch controlled by the output of said bistable device for providing said first voltage level when said output signal is present and said second voltage level when said output signal is not present; said second latch means comprises: a second bistable device controlled by said respective first and third control pulses so as to provide no output signal in response to said first control pulse and an output signal in response to said third control pulse, a second two position switch controlled by the output of said sEcond bistable device for providing said second voltage level when said output signal is present and said first voltage level when said output signal is not present; and said second voltage level is equal in magnitude to said first voltage level but of opposite polarity.

Claim 8

Binary coded digital to analog converter comprising: a n-bit buffer for storing successively different n-bit binary coded signals which are to be converted into analog signals; first clock means generating timing pulses at a first frequency for controlling the successive enterings of said different binary coded signals into said buffer, thus determining a period of time T during which each of said binary coded signals remains in said buffer, said period T including at least two equal subperiods; a (n+k)-bit counter, k being any integer, second clock means generating timing pulses at a second frequency for causing said counter to increase in value, said second frequency being at least equal to 2n k times said first frequency, detecting means for detecting the maximum value of the first n bits of the counter and providing a first control pulse each time said maximum value is detected, a digital comparator comparing at any instant the first n bits in the counter and the value in the buffer and providing a second control pulse when equality is detected, latch means controlled by said comparator output and said detecting means output, for providing a first direct voltage level in response to said first control pulse and a second direct voltage level in response to said second control pulse thereby providing a two level voltage waveform; timing means for operating said generating means during each of said subperiods, thereby providing at least two successive identical two level voltage waveforms each being representative of said current binary coded signal; means for integrating said two successive waveforms to provide an analog signal corresponding to said current binary coded signal.

Claim 9

Binary coded digital to analog converter comprising: a n-bit buffer for storing successively different n-bit binary coded signals which are to be converted into analog signals; first clock means generating timing pulses at a first frequency for controlling the successive enterings of said different binary coded signals into said buffer, thus determining a period of time T during which each of said binary coded signals remains in said buffer, said period T including at least two equal subperiods; a (n+k)-bit counter, k being any integer, second clock means generating timing pulses at a second frequency for causing said counter to increase in value, said second frequency being at least equal to 2n k times said first frequency, detecting means for detecting the maximum value of the first n bits of the counter and providing a first control pulse each time said maximum value is detected, a digital comparator comparing at any instant the first n bits in the counter and the value in the buffer and providing a second control pulse when equality is detected, latch means controlled by said comparator output and said detecting means output, for providing a first direct voltage level in response to said first control pulse and a second direct voltage level in response to said second control pulse thereby providing a two level voltage waveform; timing means for operating said generating means during each of said subperiods, thereby providing at least two successive identical two level voltage waveforms each being representative of said current binary coded signal; means for integrating said two successive waveforms to provide an analog signal corresponding to said current binary coded signal.

Claim 10

Binary coded digital to analog converter according to claim 5 wherein said latch means comprise: a bistable device controlled by said respective first and second control pulses so as to provide no output signal in response to said first control pulse and an output signal in response to said second control pulse, and a two position switch controlled by the output of said bistable device for providing said first voltage level when said output signal is present and said second voltage level when said output signal is not present, said second voltage level being equal in magnitude to said first level but of opposite polarity.

Claim 11

Binary coded digital to analog converter comprising: a n-bit buffer for storing successively different n-bit binary coded signals which are to be converted into analog signals, a (n+1)-bit counter, first clock means generating a first series of timing pulses at a first frequency for controlling the successive enterings of said binary coded signals into said buffer, second clock means the starting of which is controlled by the timing pulses of said first series, generating a second series of timing pulses at a second frequency for causing said counter to increase in value, said second frequency being at least equal to 2n 1 times said first frequency, first detecting means for detecting the 2nth state of the counter and providing a first control pulse when said state is detected, second detecting means for detecting the 2n 1th state of the counter and providing a signal for stopping said second clock means, until the occurrence of the following timing pulse of said first series, a first digital comparator comparing at any instant the value in the buffer with the first n bits in the counter, and providing a second control pulse each time an equality is detected, first latch meaNs controlled by said detecting means output and said comparator output for providing a first direct voltage level in response to said first control pulse and a second direct voltage level in response to said second control pulse thereby providing a first two level voltage waveform, a second digital comparator comparing at any instant the binary complement of the value in the buffer with the first n bits in the counter, and providing a third control pulse each time an equality is detected, second latch means controlled by said detecting means output and said second comparator output for providing said second voltage level in response to said first control pulse and said first voltage level in response to said third control pulse thereby providing a second two level voltage waveform, summing means for summing said first and second two level waveform, thereby providing a third waveform, filter means for integrating said third waveform to provide an analog signal corresponding to the current binary coded signal in the buffer.

Claim 12

Binary coded digital to analog converter comprising: a n-bit buffer for storing successively different n-bit binary coded signals which are to be converted into analog signals, a (n+1)-bit counter, first clock means generating a first series of timing pulses at a first frequency for controlling the successive enterings of said binary coded signals into said buffer, second clock means the starting of which is controlled by the timing pulses of said first series, generating a second series of timing pulses at a second frequency for causing said counter to increase in value, said second frequency being at least equal to 2n 1 times said first frequency, first detecting means for detecting the 2nth state of the counter and providing a first control pulse when said state is detected, second detecting means for detecting the 2n 1th state of the counter and providing a signal for stopping said second clock means, until the occurrence of the following timing pulse of said first series, a first digital comparator comparing at any instant the value in the buffer with the first n bits in the counter, and providing a second control pulse each time an equality is detected, first latch meaNs controlled by said detecting means output and said comparator output for providing a first direct voltage level in response to said first control pulse and a second direct voltage level in response to said second control pulse thereby providing a first two level voltage waveform, a second digital comparator comparing at any instant the binary complement of the value in the buffer with the first n bits in the counter, and providing a third control pulse each time an equality is detected, second latch means controlled by said detecting means output and said second comparator output for providing said second voltage level in response to said first control pulse and said first voltage level in response to said third control pulse thereby providing a second two level voltage waveform, summing means for summing said first and second two level waveform, thereby providing a third waveform, filter means for integrating said third waveform to provide an analog signal corresponding to the current binary coded signal in the buffer.

Claim 13

Binary coded digital to analog converter comprising: a n-bit buffer for storing successively different n-bit binary coded signals, a (n+1) bit counter, first clock means generating a first series of timing pulses at a first frequency for controlling the successive enterings of said binary coded signals into said buffer, second clock means the starting of which is controlled by the timing pulses of said first series, generating a second series of timing pulses for causing said counter to increase in value, said second frequency being equal to 2n 1 times said first frequency, first detecting means for detecting the minimum value of the first n bits in the counter and providing a first control pulse each time said minimum value is detected, second detecting means for detecting the 2n 1th state of said counter and delivering a signal for stopping said second clock means, until the occurrence of the next timing pulse of said first series, a first digital comparator comparing at any instant the value in the buffer with the first n bits in the counter, and providing a second control pulse each time equality is detected, a first bistable device controlled by said first detecting means output and said first comparator output so as to provide no output signal in response to said first control pulse and an output signal in response to said second control pulse, first gating means for gating the output signal from said first bistable device when the (n+1)th stage of said counter contains a 0, a second digital comparator comparing at any instant the binary complement of the value in the buffer with the first n bits in the counter and providing a third control pulse each time equality is detected, a second bistable device controlled by said first detecting means output and said second comparator output so as to deliver an output signal in response to said first control pulse and no output signal in response to said third control pulse, second gating means for gating the output signal from said second bistable device when the (n+1)th stage of said counter contains a 1, a two position switch controlled by the outputs of both said first and second gating means and delivering a first direct voltage level when a signal is present on anyone of said gating means outputs and a second voltage level when no signal is present on both said gating means outputs thereby providing a two voltage level waveform, and means for integrating said waveform to provide an analog signal corresponding to the current binary coded signal in the buffer.

Claim 14

Binary coded digital to analog converter comprising: a n-bit buffer for storing successively different n-bit binary coded signals, a (n+1) bit counter, first clock means generating a first series of timing pulses at a first frequency for controlling the successive enterings of said binary coded signals into said buffer, second clock means the starting of which is controlled by the timing pulses of said first series, generating a second series of timing pulses for causing said counter to increase in value, said second frequency being equal to 2n 1 times said first frequency, first detecting means for detecting the minimum value of the first n bits in the counter and providing a first control pulse each time said minimum value is detected, second detecting means for detecting the 2n 1th state of said counter and delivering a signal for stopping said second clock means, until the occurrence of the next timing pulse of said first series, a first digital comparator comparing at any instant the value in the buffer with the first n bits in the counter, and providing a second control pulse each time equality is detected, a first bistable device controlled by said first detecting means output and said first comparator output so as to provide no output signal in response to said first control pulse and an output signal in response to said second control pulse, first gating means for gating the output signal from said first bistable device when the (n+1)th stage of said counter contains a 0, a second digital comparator comparing at any instant the binary complement of the value in the buffer with the first n bits in the counter and providing a third control pulse each time equality is detected, a second bistable device controlled by said first detecting means output and said second comparator output so as to deliver an output signal in response to said first control pulse and no output signal in response to said third control pulse, second gating means for gating the output signal from said second bistable device when the (n+1)th stage of said counter contains a 1, a two position switch controlled by the outputs of both said first and second gating means and delivering a first direct voltage level when a signal is present on anyone of said gating means outputs and a second voltage level when no signal is present on both said gating means outputs thereby providing a two voltage level waveform, and means for integrating said waveform to provide an analog signal corresponding to the current binary coded signal in the buffer.