Comparison of contents of two registers

Claim 2

A comparison decision system of register contents comprising: two registers of the n-progress type each storing a numerical value content to be compared with each other; means for simultaneously applying the same constant period stepping pulses to said two registers; each of said two registers producing an output in response to an applied stepping pulse corresponding to its numerical value content; and means for receiving said outputs of said two registers in time priority and producing a comparison output signal indicating the relative magnitude of the numerical value contents of said two registers, which comparison output signal is dependent upon said time priority of said outputs of said two registers.

Claim 3

The system, as set forth in claim 1 wherein when the contents of said registers are equal, the equality of said contents of said registers is determined by a coincident output from the output of said registers.

Claim 4

The system, as set forth in claim 1, wherein said means for receiving the outputs of said registers and for producing said comparison output signal comprises: a flip-flop means operatively connected to said registers for changing the state of said flip-flop means and providing change of state output signals upon receiving the respective outputs from said registers; AND gates, each connected, respectively, for receiving said chaNge of state output signals from said flip-flop means; and means for sending a 0 reference pulse of said stepping pulses simultaneously to said AND gates.

Claim 5

The system, as set forth in claim 1, further comprising; two plural unit registers and circuit means for carrying out division by a plurality of subtractions in which the subtractions are performed from the lowest unit toward the highest unit; and said two registers of the n-progress type constituting single unit registers, and receiving readouts of corresponding units of said plural unit registers from the lowest corresponding units to the highest corresponding units, the possibility or impossibility of a subsequent subtraction being determined by the comparison decision of the numerical value contents of said single unit registers.

Claim 6

The system, as set forth in claim 1, for division by a plurality of subtractions and for determining the possibility or impossibility of subsequent subtraction by comparison between the partial remainder and the divisor, comprising: two plural unit registers and circuit means for carrying out division by a plurality of subtractions performed by adding to the dividend the same number of adding pulses as that of the complement of the divisor; said two registers of the n-progress type constituting single unit working registers and receiving readouts of corresponding units of said plural unit registers in turn from the lowest corresponding units to the highest corresponding units; and the means for receiving the outputs comprising a flip-flop for being set and reset by said outputs, respectively, the possibility or impossibility of subsequent subtraction being decided by comparison of the partial remainder and the divisor, by a comparison of said outputs of said working registers.

Claim 7

A comparison decision system of register contents, comprising: two plural unit registers each comprising a plurality of said n-progress type register units, each storing a numerical value content and constituting a plurality of ordered register units, covering from a lowest register unit to a highest register unit; means for simultaneously applying the same constant period stepping pulses to two corresponding ordered register units of said two plural unit registers; each of said two corresponding ordered register units producing an output in response to an applied stepping pulse corresponding to its numerical value content; means for receiving said outputs of said two corresponding ordered register units in time priority and producing a comparison output signal indicating the relative magnitude of the numerical value contents of said two corresponding ordered register units, which comparison output signal is dependent upon said time priority of said outputs of said two corresponding ordered register units; and means for switching said stepping pulses so that the latter are sent in turn to said plurality of corresponding ordered register units of said plural unit registers from the lowest register unit to the highest register unit.

Claim 8

A comparison decision system of register contents, comprising: two plural unit registers each comprising a plurality of said n-progress type register units, each storing a numerical value content and constituting a plurality of ordered register units, covering from a lowest register unit to a highest register unit; means for simultaneously applying the same constant period stepping pulses to two corresponding ordered register units of said two plural unit registers; each of said two corresponding ordered register units producing an output in response to an applied stepping pulse corresponding to its numerical value content; means for receiving said outputs of said two corresponding ordered register units in time priority and producing a comparison output signal indicating the relative magnitude of the numerical value contents of said two corresponding ordered register units, which comparison output signal is dependent upon said time priority of said outputs of said two corresponding ordered register units; and means for switching said stepping pulses so that the latter are sent in turn to said plurality of corresponding ordered register units of said plural unit registers from the lowest register unit to the highest register unit.

Claim 9

The system, as set forth in claim 6, wherein said means for receiving said outputs comprises a flip-flop means operatively connected to the outputs of each of said plurality of ordered register units of said plural unit registers for being set or reset in accordance with the comparative magnitude of the numerical value contents of said corresponding ordered register units of said plural unit registers, and being set or reset again in turn when said stepping pulses are switched to next corresponding ordered register units of said plural unit registers; and means for inhibiting a change in condition of said flip-flop means when the magnitude of the numerical value contents are equal in corresponding ordered register units of said plural unit registers which are then receiving said stepping pulses, whereby the relative magnitude of the ordered numerical value contents of said plural uniT registers are determined by the condition of said flip-flop means after the comparison of the highest corresponding ordered register units of said plural unit registers receiving said stepping pulses.

Claim 10

The system, as set forth in claim 7, wherein said inhibiting means includes: an AND gate operatively connected to the outputs of corresponding ordered register units of said plural unit registers; an inhibit gate connected to the output of said AND gate and to said flip-flop means; and a delay circuit connected between the outputs of said ordered register units and said inhibit gate.

Claim 11

The system, as set forth in claim 7, wherein: said switching means is a step counter; means for sending a plurality of periodic 0 reference pulses of said stepping pulses to said step counter; said step counter switching said sending of said stepping pulses in turn to said plurality of ordered register units, respectively, upon receiving each of said 0 reference pulses; and said switching means further includes a plurality of AND gates each connected at its output to one of said ordered register units, respectively, and each connected at its input to said means for applying a plurality of stepping pulses and to the output of a stage of said step counter corresponding to the respective ordered register unit to which said AND gate is connected.