Patent US3575614A successfully refreshed from Google Patents.
US3575614A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Low voltage level mos interface circuit
Assignee: Boeing North American Inc
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Filing: 1968-12-13
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Granted: 1971-04-20
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Expires: 1988-12-13
Abstract
Abstract An input MOS device has its gate electrode connected to a network for biasing the gate slightly in excess of the threshold voltage for the device. The excess bias is not greater than the maximum anticipated interface signal level which appears on the input electrode of the device. A transistor is connected to the other electrode of the device for amplifying current from the device. A second MOS device is connected in series with the transistor and a voltage source. When the input voltage is equal to or less than the excess bias voltage, the input device turns on for driving the transistor and for connecting the output electrode of the second device to ground through the transistor. When the input voltage is more than the excess bias voltage, the input device is turned off and the output electrode is driven to a usable MOS signal level.
Inventors
- 👤 Robert W Polkinghorn
- 👤 Arthur F Pfeifer
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-23 21:26
CPC Classifications
H; H03; H03K; H03K19/00; H03K19/0175; H03K19/018; H03K19/01806; H03K19/017509; H03K19/017518; H03K19/02; H03K19/08; H03K19/094; H03K19/0944; H03K19/09448; H03K19/096
Claims Analysis
Total Claims: 10
Claim 1
Independent Claim
150 words
An interfacing circuit for converting low-voltage level input signals to relatively high-voltage level output signals comprising: a first field effect transistor connected between input and output terminals and having a first control electrode; means connected to the first control electrode for biasing the first field effect transistor to turn on as a function of the input signal levels, said bias voltage being in excess of one threshold voltage of the first field effect transistor, said excess voltage being no greater than the maximum anticipated input signal levels; voltage source means; a second field effect transistor connected between said voltage source means and said output terminal and having a second control electrode; means connected to said control electrode for turning said second field effect transistor on at least during the time the input signal level on said input terminal has a magnitude less than or equal to said excess bias voltage.
Claim 2
Dependent Claim
150 words
An interfacing circuit for converting low-voltage level input signals to relatively high-voltage level output signals comprising: a first field effect transistor connected between input and output terminals and having a first control electrode; means connected to the first control electrode for biasing the first field effect transistor to turn on as a function of the input signal levels, said bias voltage being in excess of one threshold voltage of the first field effect transistor, said excess voltage being no greater than the maximum anticipated input signal levels; voltage source means; a second field effect transistor connected between said voltage source means and said output terminal and having a second control electrode; means connected to said control electrode for turning said second field effect transistor on at least during the time the input signal level on said input terminal has a magnitude less than or equal to said excess bias voltage.
Claim 3
Dependent Claim
47 words
The combination recited in claim 1 including amplifier means connected between said first field effect transistor and said output terminal for amplifying the current through said field effect transistor for reducing the effective resistance of said first field effect transistor relative to said second field effect transistor.
Claim 4
Dependent Claim
61 words
The combination recited in claim 1 including a third field effect transistor connected between said voltage source means and the inherent capacitance of the output terminal for providing charge current to said inherent capacitance when said second field effect transistor is turned off for decreasing the period required to change the output from one voltage level to a different voltage level.
Claim 5
Dependent Claim
56 words
The combination recited in claim 1 wherein said first field effect transistor has a resistance substantially less than the resistance of the second field effect transistor whereby a potential impressed across the first and second field effect transistors is substantially dropped across the second field effect transistor when the first field effect transistor is turned on.
Claim 6
Dependent Claim
70 words
The combination recited in claim 1 wherein the means for biasing includes a first field effect transistor resistor connected between said voltage source and said first control electrode, and a second field effect transistor resistor connected between said first control electrode and electrical ground for limiting the voltage on said first control electrode to said bias voltage slightly in excess of the threshold voltage of said first field effect transistor.
Claim 7
Dependent Claim
71 words
The combination recited in claim 5 wherein the means for biasing further comprises: a. amplifier means connected between said second field effect transistor resistor and said first control electrode for amplifying the current from said second field effect transistor resistor for maintaining the voltage at the control electrode at said voltage slightly in excess of said threshold voltage by pulling a relatively low current through said second field effect transistor resistor.
Claim 8
Dependent Claim
49 words
The combination recited in claim 6 including diode means connected between said first control electrode and said amplifier means for increasing the bias voltage at said first control electrode by said amount of voltage recited as being in excess of the threshold voltage of said first field effect transistor.
Claim 9
Dependent Claim
105 words
The combination recited in claim 1 including a plurality of said first field effect transistoR with each of said field effect transistors having an electrode connected to said output terminal, and with each of said field effect transistors having a separate input electrode and a control electrode, and wherein the means for biasing connected to the first control electrode of said first field effect transistor is also connected to the control electrodes of each of said plurality of field effect transistors for biasing the field effect transistors to turn on as a function of the voltage level of input signals on their respective input electrodes.
Claim 10
Dependent Claim
48 words
The combination recited in claim 8 wherein said plurality of field effect transistors are connected for implementing a noninverting logic function, with the control electrodes of the plurality of field effect transistors connected to the means for biasing, and said input electrodes receiving relatively low-voltage level input signals.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1974-04-19 | 1974-10-19 | 1975-04-20 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1978-04-19 | 1978-10-19 | 1979-04-20 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1982-04-19 | 1982-10-19 | 1983-04-20 | $7700.00 | Window Closed / Lapsed |