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US3575215A Expired / Lapsed US ⏱️ 0.0 years remaining

Pulse train extractor system

Assignee: GTE Sylvania Inc
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Filing: 1968-09-30
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Granted: 1971-04-20
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Expires: 1988-09-30
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Abstract

Abstract This system consists of a clock generator which controls the rate at which pulses of an incident pulse train are advanced through a shift register. The input to and the output of the shift register are logically combined in an AND gate. When the clock frequency is adjusted to be related to the pulse repetition frequency (PRF) of the pulses so that a pulse is in the last stage of the shift register at the same time that a succeeding pulse is received at the input thereof, the AND gate produces an output pulse. This operation is repetitive resulting in extraction of the pulse train.

Inventors

  • 👤 Ronald J Boddy

Bibliographic Details

Application Number —
Jurisdiction US
Data Source google_patents
Last Synchronized 2026-10-30 07:04
CPC Classifications
H; H03; H03K; H03K5/00; H03K5/01; H03K5/04; H03K5/05

Claims Analysis

Total Claims: 10
Claim 1
Independent Claim 232 words
Apparatus for extracting an incident pulse of a sequence of incident pulses having a particular pulse repetition frequency comprising: a first clock generator producing first clock pulses having a first clock frequency fc, first digital means comprising; first logic means responsive to incident pulses and to said first clock pulses for producing data pulses representative of receipt of associated incident pulses; and a digital delay line having n stages and responsive to said first clock pulses for entering data pulses into the first stage thereof and for advancing said entered data pulses therethrough for producing delayed data pulses corresponding to associated incident pulses, said delay line delaying said entered data pulses a predetermined time interval n/fc which is substantially equal to an integral multiple of the time interval between adjacent incident pulses having the particular pulse repetition frequency; second logic means for logically combining at least one of said delayed data pulses corresponding to an associated incident pulse and a data pulse associated with a subsequent incident pulse to extract said subsequent incident pulse when at least said one delayed data pulse and the data pulse associated with the subsequent incident pulse are simultaneously applied to said second logic means; and third logic means for logically combining extracted pulses from said second logic means and data pulses from said first logic means for producing a residue output which is the difference therebetween.
Claim 2
Dependent Claim 232 words
Apparatus for extracting an incident pulse of a sequence of incident pulses having a particular pulse repetition frequency comprising: a first clock generator producing first clock pulses having a first clock frequency fc, first digital means comprising; first logic means responsive to incident pulses and to said first clock pulses for producing data pulses representative of receipt of associated incident pulses; and a digital delay line having n stages and responsive to said first clock pulses for entering data pulses into the first stage thereof and for advancing said entered data pulses therethrough for producing delayed data pulses corresponding to associated incident pulses, said delay line delaying said entered data pulses a predetermined time interval n/fc which is substantially equal to an integral multiple of the time interval between adjacent incident pulses having the particular pulse repetition frequency; second logic means for logically combining at least one of said delayed data pulses corresponding to an associated incident pulse and a data pulse associated with a subsequent incident pulse to extract said subsequent incident pulse when at least said one delayed data pulse and the data pulse associated with the subsequent incident pulse are simultaneously applied to said second logic means; and third logic means for logically combining extracted pulses from said second logic means and data pulses from said first logic means for producing a residue output which is the difference therebetween.
Claim 3
Dependent Claim 388 words
Apparatus for extracting an incident pulse of a sequence of incident pulses having a particular pulse repetition frequency comprising: a first clock generator producing first clock pulses having a first clock frequency fc and second clock pulses having a second clock frequency; first digital delay means comprising: first logic means responsive to incident pulses and to said first clock pulses for producing data pulses representative of receipt of associated incident pulses: and a first digital delay line having n stages and responsive to said first clock pulses for entering data pulses into the first stage thereof and for advancing said entered data pulses therethrough for producing delayed data pulses corresponding to associated incident pulses, said first delay line delaying said entered data pulses a predetermined time interval n/fc which is substantially equal to an integral multiple of the time interval between adjacent incident pulses having the particulAr pulse repetition frequency; second logic means for logically combining at least one of said delayed data pulses from said first delay line corresponding to an associated incident pulse and a data pulse associated with a subsequent incident pulse to extract said subsequent incident pulse when at least said one delayed data pulse and the data pulse associated with the subsequent incident pulse are simultaneously applied to said second logic means: third logic means for logically combining extracted pulses from said second logic means and data pulses from said first logic means for producing a residue output which is the difference therebetween; a second digital delay line having a plurality of stages and being responsive to said second clock pulses for entering residue pulses from said third logic means in the first stage of said second delay line and for advancing entered residue pulses therethrough, said second delay line delaying said entered residue pulses a time interval different from the delay of said data pulses provided by said first delay line for extracting incident pulses having a pulse repetition frequency different from the particular pulse repetition frequency; and fourth logic means logically combining at least one of said delayed residue pulses corresponding to an associated incident pulse and a subsequent residue pulse corresponding to a subsequent incident pulse for extracting said subsequent incident pulse when a delayed residue pulse and a subsequent residue pulse are simultaneously applied to said fourth logic means.
Claim 4
Dependent Claim 388 words
Apparatus for extracting an incident pulse of a sequence of incident pulses having a particular pulse repetition frequency comprising: a first clock generator producing first clock pulses having a first clock frequency fc and second clock pulses having a second clock frequency; first digital delay means comprising: first logic means responsive to incident pulses and to said first clock pulses for producing data pulses representative of receipt of associated incident pulses: and a first digital delay line having n stages and responsive to said first clock pulses for entering data pulses into the first stage thereof and for advancing said entered data pulses therethrough for producing delayed data pulses corresponding to associated incident pulses, said first delay line delaying said entered data pulses a predetermined time interval n/fc which is substantially equal to an integral multiple of the time interval between adjacent incident pulses having the particulAr pulse repetition frequency; second logic means for logically combining at least one of said delayed data pulses from said first delay line corresponding to an associated incident pulse and a data pulse associated with a subsequent incident pulse to extract said subsequent incident pulse when at least said one delayed data pulse and the data pulse associated with the subsequent incident pulse are simultaneously applied to said second logic means: third logic means for logically combining extracted pulses from said second logic means and data pulses from said first logic means for producing a residue output which is the difference therebetween; a second digital delay line having a plurality of stages and being responsive to said second clock pulses for entering residue pulses from said third logic means in the first stage of said second delay line and for advancing entered residue pulses therethrough, said second delay line delaying said entered residue pulses a time interval different from the delay of said data pulses provided by said first delay line for extracting incident pulses having a pulse repetition frequency different from the particular pulse repetition frequency; and fourth logic means logically combining at least one of said delayed residue pulses corresponding to an associated incident pulse and a subsequent residue pulse corresponding to a subsequent incident pulse for extracting said subsequent incident pulse when a delayed residue pulse and a subsequent residue pulse are simultaneously applied to said fourth logic means.
Claim 5
Dependent Claim 201 words
Apparatus for extracting an incident pulse of a sequence of incident pulses having a particular pulse repetition frequency comprising: a first clock generator producing first clock pulses having a first clock frequency fc; first digital delay means comprising: first logic means responsive to incident pulses and to said first clock pulses for producing data pulses representative of receipt of associated incident pulses; and a plurality of digital delay lines each having a plurality of stages, a particular one of said delay lines being responsive to first clock pulses for entering data pulses in the first stage thereof and for advancing entered data pulses therethrough for producing delayed data pulses corresponding to associated input pulses, each other one of said delay lines being responsive to first clock pulses for entering in the first stage thereof delayed data pulses from a different associated one of said delay lines; and second logic means for logically combining data pulses and delayed data pulses from each one of said delay lines for extracting the incident pulse associated with one data pulse when the one data pulse and delayed data pulses from a prescribed number of said delay lines are simultaneously applied to said second logic means.
Claim 6
Dependent Claim 201 words
Apparatus for extracting an incident pulse of a sequence of incident pulses having a particular pulse repetition frequency comprising: a first clock generator producing first clock pulses having a first clock frequency fc; first digital delay means comprising: first logic means responsive to incident pulses and to said first clock pulses for producing data pulses representative of receipt of associated incident pulses; and a plurality of digital delay lines each having a plurality of stages, a particular one of said delay lines being responsive to first clock pulses for entering data pulses in the first stage thereof and for advancing entered data pulses therethrough for producing delayed data pulses corresponding to associated input pulses, each other one of said delay lines being responsive to first clock pulses for entering in the first stage thereof delayed data pulses from a different associated one of said delay lines; and second logic means for logically combining data pulses and delayed data pulses from each one of said delay lines for extracting the incident pulse associated with one data pulse when the one data pulse and delayed data pulses from a prescribed number of said delay lines are simultaneously applied to said second logic means.
Claim 7
Dependent Claim 240 words
Apparatus for extracting a train of incident pulses from a sequence of incident pulses having a particular pulse repetition frequency comprising: a first clock generator producing first clock pulses having a first clock frequency fc; first digital delay means comprising: first logic means responsive to incident pulses and to said first clock pulses for producing data pulses representative of receipt of associated incident pulses; and a digital delay line having n stages and responsive to said first clock pulses for entering data pulses into the first stage thereof and for advancing said entered data pulses therethrough for producing delayed data pulses corresponding to associated input pulses, said delay line delaying said entered data pulses a predetermined time interval n/fc which is substantially equal to an integral multiple of the time interval between adjacent incident pulses having the particular pulse repetition frequency; second logic means for logically combining at least one of said delayed data pulses corresponding to an associated incident pulse And a data pulse associated with a subsequent incident pulse to extract said subsequent incident pulse when at least said one delayed data pulse and the data pulse associated with the subsequent incident pulse are simultaneously applied to said second logic means; and means responsive to said first clock pulses and said extracted pulses for indicating whether the pulse repetition frequency of the train of extracted pulses is equal to the predetermined frequency fc/n or an integral multiple thereof.
Claim 8
Dependent Claim 240 words
Apparatus for extracting a train of incident pulses from a sequence of incident pulses having a particular pulse repetition frequency comprising: a first clock generator producing first clock pulses having a first clock frequency fc; first digital delay means comprising: first logic means responsive to incident pulses and to said first clock pulses for producing data pulses representative of receipt of associated incident pulses; and a digital delay line having n stages and responsive to said first clock pulses for entering data pulses into the first stage thereof and for advancing said entered data pulses therethrough for producing delayed data pulses corresponding to associated input pulses, said delay line delaying said entered data pulses a predetermined time interval n/fc which is substantially equal to an integral multiple of the time interval between adjacent incident pulses having the particular pulse repetition frequency; second logic means for logically combining at least one of said delayed data pulses corresponding to an associated incident pulse And a data pulse associated with a subsequent incident pulse to extract said subsequent incident pulse when at least said one delayed data pulse and the data pulse associated with the subsequent incident pulse are simultaneously applied to said second logic means; and means responsive to said first clock pulses and said extracted pulses for indicating whether the pulse repetition frequency of the train of extracted pulses is equal to the predetermined frequency fc/n or an integral multiple thereof.
Claim 9
Dependent Claim 321 words
Apparatus extracting an incident pulse of a sequence of incident pulses having a prescribed pulse repetition frequency comprising: a second clock generator producing clock pulses; fifth logic means responsive to incident pulses and to clock pulses for producing data pulses representative of receipt of associated incident pulses; a fifth plurality of digital delay lines each having a plurality of stages, a particular one of said fifth delay lines being responsive to clock pulses for entering data pulses into the first stage thereof and for advancing entered data pulses therethrough, each other one of said fifth delay lines being responsive to clock pulses for entering into the first stage thereof delayed data pulses from the nth stage (where n is an integer) of a different associated one of said fifth delay lines; a sixth plurality of logic circuits, each sixth logic circuit being responsive to delayed data pulses from at least the n-1th, nth, and n+1hu th stages of an associated other one of said fifth delay lines for producing an output pulse if at least one delayed data pulse from one of said stages is applied thereto; a seventh plurality of logic circuits, a particular one of said seventh logic circuits being responsive to delayed data pulses from the nth stage of said one particular line of said fifth delay lines and the output pulses from each one of said sixth logic circuits, the other ones of said seventh logic circuits each being responsive to delayed data pulses from the same stage of each line of said fifth delay lines, said seventh logic circuits individually producing an output pulse when pulses are simultaneously applied to each input of the associated individual seventh logic circuit; and eighth logic means extracting an incident pulse associated with a data pulse when the data pulse and an output pulse from any one of said seventh logic circuits are simultaneously applied to said eighth logic means.
Claim 10
Dependent Claim 321 words
Apparatus extracting an incident pulse of a sequence of incident pulses having a prescribed pulse repetition frequency comprising: a second clock generator producing clock pulses; fifth logic means responsive to incident pulses and to clock pulses for producing data pulses representative of receipt of associated incident pulses; a fifth plurality of digital delay lines each having a plurality of stages, a particular one of said fifth delay lines being responsive to clock pulses for entering data pulses into the first stage thereof and for advancing entered data pulses therethrough, each other one of said fifth delay lines being responsive to clock pulses for entering into the first stage thereof delayed data pulses from the nth stage (where n is an integer) of a different associated one of said fifth delay lines; a sixth plurality of logic circuits, each sixth logic circuit being responsive to delayed data pulses from at least the n-1th, nth, and n+1hu th stages of an associated other one of said fifth delay lines for producing an output pulse if at least one delayed data pulse from one of said stages is applied thereto; a seventh plurality of logic circuits, a particular one of said seventh logic circuits being responsive to delayed data pulses from the nth stage of said one particular line of said fifth delay lines and the output pulses from each one of said sixth logic circuits, the other ones of said seventh logic circuits each being responsive to delayed data pulses from the same stage of each line of said fifth delay lines, said seventh logic circuits individually producing an output pulse when pulses are simultaneously applied to each input of the associated individual seventh logic circuit; and eighth logic means extracting an incident pulse associated with a data pulse when the data pulse and an output pulse from any one of said seventh logic circuits are simultaneously applied to said eighth logic means.

References Cited (Backward Citations)

US3047806A Cited
US2980858A Cited
US3209265A Cited
US3238462A Cited
US3423728A Cited

USPTO Annuity & Maintenance Windows

Annuity Stage Window Opens Payment Deadline Surcharge Period Until Estimated Fee Status
3.5 Years (Year 4) 1974-04-19 1974-10-19 1975-04-20 $2000.00 Window Closed / Lapsed
7.5 Years (Year 8) 1978-04-19 1978-10-19 1979-04-20 $3760.00 Window Closed / Lapsed
11.5 Years (Year 12) 1982-04-19 1982-10-19 1983-04-20 $7700.00 Window Closed / Lapsed

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