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US3573797A
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Rate augmented digital-to-analog converter
Assignee: National Aeronautics and Space Administration
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Filing: 1968-10-24
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Granted: 1971-04-06
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Expires: 1988-10-24
Abstract
Abstract This disclosure describes a rate augmented digital-to-analog converter for computed time-dependent data. The converter produces a smooth continuous function by digitally incrementing functions samples at a rate proportion to a predicted functional change over each sample interval. The result is continuously converted to an analog voltage. The conversion produces an output which is, in effect, the sum of a linear ramp and the function sample. The converter input data are the computed sample and the change which is predicted by the solution of an nth-order extrapolation formula. The computer providing the function change information to the converter also solves the nth-order extrapolation formula.
Inventors
- 👤 Sheldon Kopelson
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-04 08:48
CPC Classifications
G; G06; G06F; G06F7/00; G06F7/60; G06F7/64; G06F7/66; H; H03; H03M; H03M1/00; H03M1/12; H03M1/48
Claims Analysis
Total Claims: 9
Claim 1
Independent Claim
270 words
A rate augmented digital-to-analog converter comprising: a first register for registering digital function data; a second register for registering predicted digital function data changes; up/down counter means controllable to count up and count down in accordance with input signals connected to said first and second registers to count up and count down the input from said first register in accordance with the signal from said second register; transfer means connected between said first register and said up/down counter for transferring digital function data from said first register to said up/down counter; a third register connected to said second register for reading out the predicted digital function data changes in said second register; control means connected to said transfer means and said third register for controlling the transfer of data from said first register to said up/down counter means and the transfer of data from said second register to the third register; a channel binary rate multiplier having a first input connected to said control means and a second input connected to said third register; a control and overflow inhibitor having a first input connected to the output of said up/down counter, a second input connected to an output of said third register, and a third input connected to the output of said channel binary rate multiplier, and having its outputs connected to the control and pulse inputs of said up/down counter so as to be able to change the count in said up/down counter; and digital-to-analog converter means connected to the output of said up/down counter means for converting the output from said up/down counter means into an analog signal.
Claim 2
Dependent Claim
270 words
A rate augmented digital-to-analog converter comprising: a first register for registering digital function data; a second register for registering predicted digital function data changes; up/down counter means controllable to count up and count down in accordance with input signals connected to said first and second registers to count up and count down the input from said first register in accordance with the signal from said second register; transfer means connected between said first register and said up/down counter for transferring digital function data from said first register to said up/down counter; a third register connected to said second register for reading out the predicted digital function data changes in said second register; control means connected to said transfer means and said third register for controlling the transfer of data from said first register to said up/down counter means and the transfer of data from said second register to the third register; a channel binary rate multiplier having a first input connected to said control means and a second input connected to said third register; a control and overflow inhibitor having a first input connected to the output of said up/down counter, a second input connected to an output of said third register, and a third input connected to the output of said channel binary rate multiplier, and having its outputs connected to the control and pulse inputs of said up/down counter so as to be able to change the count in said up/down counter; and digital-to-analog converter means connected to the output of said up/down counter means for converting the output from said up/down counter means into an analog signal.
Claim 3
Dependent Claim
58 words
A rate augmented digital-to-analog converter as claimed in claim 1 wherein said third register is connected to a one''s complementer, said one''s complementer having a sign output and a magnitude output, said sign output connected to an input of said control and overflow inhibitor and said magnitude output connected to an input of said channel binary rate multiplier.
Claim 4
Dependent Claim
145 words
A rate augmented digital-to-analog converter as claimed in claim 2 wherein said control means comprises: a synchronous controller connected so as to receive a control signal at a first input; said synchronous controller having outputs connected to said transfer means, said third register and said channel binary rate multiplier; a pulse oscillator having an output connected to a second input of said synchronous controller; a gate having a signal input connected to the output of said pulse oscillator and inhibit input connected to an output of said synchronous controller; a system binary rate multiplier having a first input connected to the output of said gate and a second input connected to the output of said synchronous controller and an output connected to said channel binary rate multiplier; and interval ratio switches having an output connected to a third input of said system binary rate multiplier.
Claim 5
Dependent Claim
63 words
A rate augmented digital-to-analog converter as clAimed in claim 3 including means for connecting the date outputs of a tape reader and address decoded to the date inputs of said first and second registers and the control outputs of said tape reader and address decoder to the control inputs of said first and second register and the control input of said synchronous controller.
Claim 6
Dependent Claim
71 words
A rate augmented digital-to-analog converter as claimed in claim 1 including a channel binary rate selector-combiner, one input connected to a magnitude output of said register and an output connected to said control and overflow inhibitor, said third register having a sign output connected directly to said control and overflow inhibitor, said channel binary rate selector and combiner having a plurality of inputs connected to predetermined outputs of said control means.
Claim 7
Dependent Claim
55 words
A rate augmented digital-to-analog converter as claimed in claim 5 including: one''s complementer for receiving data and for applying it to said first and second registers; and an address decoder for receiving address data and having a plurality of control outputs connected to said one''s complementer, said first and second register, and said control means.
Claim 8
Dependent Claim
202 words
A rate augmented digital-to-analog converter as claimed in claim 6 wherein said control means comprises: a synchronous controller having a control input connected to an output of said address decoder and having an output connected to said transfer means and said third register; a pulse oscillator having an output connected to said synchronous controller; A gate having a signal input connected to the output of said pulse oscillator and an inhibit input connected to an output of said synchronous controller; a binary rate multiplier having a signal input connected to the output of said gate and a reset input connected to an output of said synchronous controller; an interval rate ratio register having an input connected to an output of said one''s complementer and a control input connected to an input of said address decoder, and having an output connected to an input of said binary rate multiplier; a binary rate generator having a reset input connected to an output of said synchronous controller and a signal input connected to the output of said binary rate multiplier; and a set of digital amplifiers having inputs connected to outputs of said binary rate generator and outputs connected to said channel binary rate selector-combiner.
Claim 9
Dependent Claim
37 words
A rate augmented digital-to-analog converter as claimed in claim 7 wherein said predicted digital function data changes are determined by the solution of a predetermined equation which equation results from data derived from prior digital function data.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1974-04-05 | 1974-10-05 | 1975-04-06 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1978-04-05 | 1978-10-05 | 1979-04-06 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1982-04-05 | 1982-10-05 | 1983-04-06 | $7700.00 | Window Closed / Lapsed |