Associative memory circuitry

Claim 2

An associative memory cell including, in combination: a memory circuit portion with first and second transistors, each having four electrodes including two input electrodes for receiving digital logic signals, three of the electrodes of said transistors including one input electrode being cross coupled in a bistable circuit configuration so that said first and second transistors alternately conduct as the memory circuit portion is switched from one to the other of two stable conductive states; said first input electrodes of said first and second transistors respectively connected to a word select line to which a predetermined potential is applied when the memory cell is selected and when it is desired to either write data into the cell or to sense the binary state of the cell; said second input electrodes of each of said first and second transistors connected to sense-write input terminals and adapted to receive thereat a potential sufficient in magnitude to change the bistable state of the memory cell when data is written into the cell, and said first and second transistors conducting current through the sense-write terminals to sense circuitry when the conductive state of the cell is read; and association current switch circuit means connected between said first and second transistors and an associative sense terminal, said association current switch circuit means further connected to said sense-write terminals and responsive to the potential at said sense-write terminals and to the conductive state of said first and second transistors to indicate a match or a mismatch between the conductive state of the memory cell and the conductive state of the sense-write circuitry by either conducting current from the associative sense terminal or remaining nonconductive.

Claim 3

The associative memory cell defined in claim 1 in combination with a sense-write circuit which is connected via first and second data lines to said second input electrodes of said first and second transistors, respectively, in the associative memory cell, said sense-write circuit providing differential data on said first and second data lines for changing the conductive state of the associative memory cell, and said associative memory cell conducting current through said first and second data lines to said sense-write circuit so that said sense-write circuit is operative to determine the conductiVe state of said associative memory cell.

Claim 4

The combination defined in claim 2 which further includes: first and second data input terminals connected to said sense-write circuit for receiving binary input signals; and first and second binary output terminals connected to said sense-write circuit for providing output signals in response to potentials on said first and second data lines and to binary signals applied to said first and second input terminals of said sense-write circuit. 4. The memory cell defined in claim 1 wherein: said association current switch circuit means includes a third transistor connected between said associative sense terminal and said first transistor and conducting current to indicate nonassociation between the bistable state of the memory cell and the bistable state of the sense-write circuitry; and a fourth transistor connected between said associative sense terminal and said second transistor and conducting current to indicate nonassociation between the binary state of said memory cell and the binary state of said sense-write circuitry.

Claim 5

The memory cell defined in claim 4 wherein said input electrodes of each of said first and second transistors comprise a first and a second emitter; the base electrodes of the first and second transistors cross connected, respectively, through resistors to the collector electrodes of the second and first transistors to ensure proper bistable operation of said memory circuit.

Claim 6

The memory cell defined in claim 5 wherein: the first emitter of each of the first and second transistors is connected to a word select terminal and receiving thereat a potential sufficient in magnitude to permit the conductive state of the memory cell to be changed, sensed or inhibited; and the second emitter of each of the first and second transistors connected to the base of the third and fourth transistors, respectively, and to the sense-write input terminals so that the conductivity of the first and third transistors is controlled by the potential on the sense-write input terminals and the conductive state of said memory circuit.

Claim 7

The memory cell defined in claim 6 which further includes third and fourth resistors connected between a voltage supply terminal and said first and second resistors, respectively, and providing a current path from said voltage supply terminal to said first and second transistors during the operation of the associative memory cell.

Claim 8

An associative memory cell including, in combination: a memory circuit portion with first and second transistors cross coupled in a bistable circuit configuration so that said first and second transistors alternately conduct as the memory circuit portion is switched from one to the other of two stable conductive states; said first and second transistors each having first and second input electrodes for receiving digital logic signals; said first input electrodes of said first and second transistors respectively connected to a word select line to which a predetermined potential is applied when the memory cell is selected and when it is desired to either write data into the cell or to sense the binary state of the cell; said second input electrodes of each of said first and second transistors connected to sense-write input terminals and adapted to receive thereat a potential sufficient in magnitude to change the bistable state of the memory cell when data is written into the cell, and said first and second transistors conducting current through the sense-write terminals to sense circuitry when the conductive state of the cell is read; association current switch circuit means connected between said first and second transistors and an associative sense terminal, said association current switch circuit means further connected to said sense-write terminals and responsive to the potential at said sense-write terminals and to the conductive state of said first and second transistors to indicate a match or a mismatch between the conductive state of the memory cell and the conductive state of the sense-write circuitry by either conducting current from the associative sense terminal or remaining nonconductive; said association current switch circuit means includes a third transistor connected between said associative sense terminal and said first transistor and conducting current to indicate nonassociation between the bistable state of the memory cell and the bistable state of the sense-write circuitry; a fourth transistor connected between said associative sense terminal and said second transistor and conducting current to indicate nonassociation between the binary state of said memory cell and the binary state of said sense-write circuitry; a first level shifting resistor connected between said first and third transistors and provides a desired DC level shift therebetween during the operation of the memory cell; and a second level shifting resistor connected between said second and fourth transistors and provides a desired DC level shift therebetween during the operation of said memory cell.

Claim 9

An associative memory cell including, in combination: a memory circuit portion with first and second transistors cross coupled in a bistable circuit configuration so that said first and second transistors alternately conduct as the memory circuit portion is switched from one to the other of two stable conductive states; said first and second transistors each having first and second input electrodes for receiving digital logic signals; said first input electrodes of said first and second transistors respectively connected to a word select line to which a predetermined potential is applied when the memory cell is selected and when it is desired to either write data into the cell or to sense the binary state of the cell; said second input electrodes of each of said first and second transistors connected to sense-write input terminals and adapted to receive thereat a potential sufficient in magnitude to change the bistable state of the memory cell when data is written into the cell, and said first and second transistors conducting current through the sense-write terminals to sense circuitry when the conductive state of the cell is read; association current switch circuit means connected between said first and second transistors and an associative sense terminal, said association current switch circuit means further connected to said sense-write terminals and responsive to the potential at said sense-write terminals and to the conductive state of said first and second transistors to indicate a match or a mismatch between the conductive state of the memory cell and the conductive state of the sense-write circuitry by either conducting current from the associative sense terminal or remaining nonconductive; said association current switch circuit means includes a third transistor connected between said associative sense terminal and said first transistor and conducting current to indicate nonassociation between the bistable state of the memory cell and the bistable state of the sense-write circuitry; a fourth transistor connected between said associative sense terminal and said second transistor and conducting current to indicate nonassociation between the binary state of said memory cell and the binary state of said sense-write circuitry; a first level shifting resistor connected between said first and third transistors and provides a desired DC level shift therebetween during the operation of the memory cell; and a second level shifting resistor connected between said second and fourth transistors and provides a desired DC level shift therebetween during the operation of said memory cell.