Data registration system

Claim 2

In a plural order register for receiving a data word represented by a timewise staggered sequence of data signals with the signals comprising a first portion of said word being concurrent with each other for a time less than the duration of any one signal and with the signals comprising a second portion of said word being concurrent with each other for a time less than the duration of any one signal, register means, means responsive to the concurrence of the signals comprising a first portion of a received word for generating an output signal indicating whether an identity exists between the signals comprising said first portion and the corresponding portion of a word currently stored in said register means from a preceding reception of data signals, and means responsive to the concurrence of the signals comprising a second portion of said word for generating an output signal indicating whether an identity exists between the signals comprising said second portion and the corresponding portion of said word currently stored in said register means.

Claim 3

In a plural order data registration system, means for receiving repeated transmissions of a data word having a first and a second portion and represented by a timewise staggered sequence of signals in which all signals comprising each portion are concurrent with each other but not with all signals of the other portion, a register, means responsive to a first reception of a word for entering said word into said register, a comparison circuit for receiving the signals comprising a subsequent transmIssion of said word, and means including said comparison circuit responsive to the concurrence of the retransmitted signals comprising each portion of said word for generating separate output signals indicating whether an identity exists between each portion of said retransmitted word and the corresponding portion of the word in said register.

Claim 4

In a plural order data registration system, means for receiving repeated transmissions of a data word having a first and a second portion and represented by a timewise staggered sequence of signals in which all signals comprising each portion are concurrent with each other but not with all signals of the other portion, a register, means responsive to a first reception of a word for entering said word into said register, a comparison circuit for receiving the signals comprising a subsequent transmIssion of said word, and means including said comparison circuit responsive to the concurrence of the retransmitted signals comprising each portion of said word for generating separate output signals indicating whether an identity exists between each portion of said retransmitted word and the corresponding portion of the word in said register.

Claim 5

The invention of claim 2 in combination with means responsive to said output signals for generating a control signal indicating whether an identity exists between the entirety of a registered and a currently received word.

Claim 6

The invention of claim 3 in combination with means responsive to a signal indicating that said received and said registered words are not identical for resetting said register so that the word represented by the next transmission of data signals may be entered into said register.

Claim 7

In a data registration system for receiving repeated transmissions of a data word represented by a timewise staggered sequence of signals with each signal being concurrent with some but less than all of the signals comprising said sequence, a register, means responsive to the first reception of a word for entering said word into said register, a comparison circuit having a first and a second portion, means including said first portion of said comparison circuit responsive to the concurrence of a first received and an intermediate received signal of said sequence on a subsequent transmission of a word for generating an output signal indicating whether an identity exists between the portion of the word represented by said first through said intermediate signals of said sequence and the corresponding portion of the word currently stored in said register, and means including said second portion of said comparison circuit responsive to the concurrence of an intermediate and a last received signal of said sequence on said subsequent transmission for generating an output signal indicating whether an identity exists between the portion of the word represented by said intermediate through the last signals of said sequence and the corresponding portion of the word currently stored in said register.

Claim 8

In a data registration system for receiving repeated transmissions of a data word represented by a timewise staggered sequence of signals with each signal being concurrent with some but less than all of the signals comprising said sequence, a register, means responsive to the first reception of a word for entering said word into said register, a comparison circuit having a first and a second portion, means including said first portion of said comparison circuit responsive to the concurrence of a first received and an intermediate received signal of said sequence on a subsequent transmission of a word for generating an output signal indicating whether an identity exists between the portion of the word represented by said first through said intermediate signals of said sequence and the corresponding portion of the word currently stored in said register, and means including said second portion of said comparison circuit responsive to the concurrence of an intermediate and a last received signal of said sequence on said subsequent transmission for generating an output signal indicating whether an identity exists between the portion of the word represented by said intermediate through the last signals of said sequence and the corresponding portion of the word currently stored in said register.

Claim 9

In a plural order data registration system for receiving a data word represented by a timewise staggered sequence of signals with each signal being concurrent with some but not all of the signals comprising said sequence, an input conductor individual to each order of said system, a register, means for repeatedly applying to said input conductors the signals representing each data word that is to be registered, means responsive to a first reception of a data word for entering it into said register, a comparison circuit, means for applying the signals representing each received data word to said comparison circuit, means responsive to the concurrence of a first received and an intermediate received signal of said sequence on a subsequent reception of said word for generating an output signal indicating whether an identity exists between the portion of a word represented by said first through said intermediate signals of said sequence and the corresponding portion of the word currently stored in said register, and means responsive to the concurrence of an intermediate and a last received signal of said sequence on said subsequent reception for generating an output signal indicating whether an identity exists between the portion of a word represented by said intermediate through the last signals of said sequence and the corresponding portion of the word currently stored in said register.

Claim 10

In a plural order data registration system for receiving a data word represented by a timewise staggered sequence of signals with each signal being concurrent with some but not all of the signals comprising said sequence, an input conductor individual to each order of said system, a register, means for repeatedly applying to said input conductors the signals representing each data word that is to be registered, means responsive to a first reception of a data word for entering it into said register, a comparison circuit, means for applying the signals representing each received data word to said comparison circuit, means responsive to the concurrence of a first received and an intermediate received signal of said sequence on a subsequent reception of said word for generating an output signal indicating whether an identity exists between the portion of a word represented by said first through said intermediate signals of said sequence and the corresponding portion of the word currently stored in said register, and means responsive to the concurrence of an intermediate and a last received signal of said sequence on said subsequent reception for generating an output signal indicating whether an identity exists between the portion of a word represented by said intermediate through the last signals of said sequence and the corresponding portion of the word currently stored in said register.

Claim 11

The invention of claim 6 in combination with means responsive to said last-named output signal for generating a control signal indicating whether an identity exists between the entirety of a registered and said currently received word.

Claim 12

The invention of claim 7 in combination with means responsive to said control signal when an identity does not exist between a currently received and a registered word for resetting said register so that the word received on the next transmission may be entered therein.

Claim 13

In a plural order data registration system for receiving a data word represented by a timewise staggered sequence of signals with each signal being concurrent with at least the adjacent signals of said sequence but with less than all of the other signals of said sequence, an input conductor individual to each order of said system, means for repeatedly applying to said input conductors the signals representing each data word that is to be registered, a plurality of normally inhibited gates each of which is individually connected to one of said input conductors, means responsive during the reception of a word for initially enabling said gates when a first signal of a newly received sequence representing said word is not concurrent with the last signal of a preceding sequence, a plural order register, and means connecting each register order to the output of an individual one of said gates so that the signals applied to said gates when in an enabled condition may be entered into said register.

Claim 14

In a plural order data registration system for receiving a data word represented by a timewise staggered sequence of signals with each signal being concurrent with at least the adjacent signals of said sequence but with less than all of the other signals of said sequence, an input conductor individual to each order of said system, means for repeatedly applying to said input conductors the signals representing each data word that is to be registered, a plurality of normally inhibited gates each of which is individually connected to one of said input conductors, means responsive during the reception of a word for initially enabling said gates when a first signal of a newly received sequence representing said word is not concurrent with the last signal of a preceding sequence, a plural order register, and means connecting each register order to the output of an individual one of said gates so that the signals applied to said gates when in an enabled condition may be entered into said register.

Claim 15

The invention of claim 9 in combination with means responsive to the entry of a word into said register for inhibiting said gates to prevent the passage of subsequently received data signals therethrough.

Claim 16

The invention of claim 10 in which said last-named means comprises, a parity check circuit responsive to the registration of a word in said register for generating a signal indicating whether said word is registered with good parity, and means responsive to said good parity signal for applying an inhibiting potential to said gates.

Claim 17

The invention of claim 11 in combination with means responsive to a signal indicating bad parity for resetting said register so that the word represented by the next application of a signal to said input conductors may be entered into said register.

Claim 18

The invention of claim 12 in combination with comparison means responsive to an indication of good parity for determining whether an identity exists between the word represented by the signals next applied to said input conductors and the word currently in said register.

Claim 19

The invention of claim 13 in combination with means responsive to the concurrence of a first received and an intermediate received signal of said next received sequence for generating a signal indicating whether an identity is found by said comparison circuit on that portion of said word represented by all the signals therebetween, means responsive to the concurrence of an intermediate and a last received signal of said next received sequence for generating a signal indicating whether an identity is found by said comparison circuit on that portion of said word represented by all signals therebetween, and means responsive to said last-named signal for generating a signal indicating whether an identity is found by said comparison circuit for all of said word.

Claim 20

The invention of claim 14 in combination with means responsive to a signal indicating that said received and registered words are not identical for resetting said register and for enabling said gates.

Claim 21

The invention of claim 14 in combination with means responsive to the termination of the repeated application of signals to one of said input conductors for resetting said register.