Abstract A capacitive pullup, two-phase shift register formed by Pchannel enhancement mode MOS transistors is disclosed as the embodiment of the invention. As a result of the capacitive coupling, a P-type diffusion which is normally negative will go positive in some instances. This forward biases the normally reverse biased PN junction between the P-type diffusion and the N-type substrate, injecting carriers into the substrate which may be collected at any other negatively biased P-type diffusion which then functions as the collector of a bipolar transistor. This collector current may result in the loss of stored logic information. To minimize these effects, a P-type collector diffusion is disposed adjacent to each potential emitting diffusion to collect the spurious carriers injected into the substrate before they cause the loss of stored data.
An integrated circuit as defined in claim 1 wherein said fourth diffused region is an integral with and an extension of said first diffused region and completely surrounding said second and third diffused regions.
Claim 2
Dependent Claim
28 words
An integrated circuit as defined in claim 2 wherein said substrate is N-type, the diffused regions are P-type and the field effect transistors are enhancement mode P-channel devices.
Claim 3
Dependent Claim
27 words
An integrated circuit as defined in claim 2 wherein said substrate is P-type, the diffused regions are N-type and the field-effect transistors are N-channel enhancement mode devices.
Claim 4
Dependent Claim
66 words
An integrated circuit as defined in claim 2 and further including a plurality of cells comprising fifth, sixth and seventh diffused regions defining with said oxide and said metal film third and fourth field effect transistors and a second capacitor and a portion of said fourth diffused region is interposed between said first, second, and third diffused regions and said fifth, sixth, and seventh diffused regions.
Claim 5
Dependent Claim
28 words
An integrated circuit as defined in claim 5 wherein said transistors and capacitors are connected together by said metal film to form a 2-phase, capacitive pullup shift register.