Patent US3573505A successfully refreshed from Google Patents.
US3573505A
Expired / Lapsed
US
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Bistable circuit and memory cell
Assignee: International Business Machines Corp
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Filing: 1968-07-15
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Granted: 1971-04-06
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Expires: 1988-07-15
Abstract
Abstract A memory cell in which the load devices thereof are unidirectional devices such as diodes, In the cell, where the storage devices are PNP or NPN devices, the diode load devices are disposed in the circuit such that the PN junctions of the diodes are backward biased. The storage devices, which are crosscoupled, and the diode load devices are connected at nodes to which gated drivers are also connected for the purpose of applying appropriate voltages to the nodes and, therefore, to the gate electrodes of the storage devices to change the conducting state of the storage devices during an active state. The gated drivers when turned on, also provide a portion of a current path to detect the conducting state of one or the other of the storage devices. In a quiescent state, the diode load devices in conjunction with a backward-biased PN junction portion of the OFF storage device form a nonlinear voltage divider which, because of their relative impedances, apply a voltage at the node of the OFF storage device to which the gate of the ON storage device is connected which maintains that storage device in the ON condition during the quiescent state. A bistable circuit and a nondestructive readout memory array are also disclosed.
Inventors
- 👤 Fritz H Gaensslen
- 👤 Dominic P Spampinato
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-30 14:46
CPC Classifications
H; H03; H03K; H03K3/00; H03K3/02; H03K3/353; H03K3/356; H03K3/356017; H03K3/356052; H03K3/35606; G; G11; G11C; G11C11/00; G11C11/21; G11C11/34; G11C11/40; G11C11/41; G11C11/412
Claims Analysis
Total Claims: 15
Claim 1
Independent Claim
15 words
A memory cell according to claim 1 wherein said pair of transistors are unipolar transistors.
Claim 2
Dependent Claim
15 words
A memory cell according to claim 1 wherein said pair of transistors are NPN transistors.
Claim 3
Dependent Claim
15 words
A memory cell according to claim 1 wherein said pair of transistors are PNP transistors.
Claim 4
Dependent Claim
46 words
A memory cell according to claim 1 wherein said means for causing one of said pair to assume one of an OFF and ON condition includes gating means for applying varying voltages to said transistors to cause one of said like pair of transistors to conduct.
Claim 5
Dependent Claim
30 words
A memory cell according to claim 1 further including means coupled to said transistors to detect one of a voltage and a current through at least one of said transistors.
Claim 6
Dependent Claim
20 words
A memory cell according to claim 5 wherein said gating means is a diode connected to each of said transistors.
Claim 7
Dependent Claim
19 words
A memory cell according to claim 1 further including at least a voltage source connected to said leakage means.
Claim 8
Dependent Claim
38 words
A memory cell according to claim 1 wherein said means for causing one of said pair to assume one of an OFF and ON condition includes a driver transistor connected to each of said pair of cross-coupled transistors.
Claim 9
Dependent Claim
15 words
A memory cell according to claim 1 wherein said unidirectional means is a backward-biased diode.
Claim 10
Dependent Claim
31 words
A memory cell according to claim 9 wherein said leakage means further includes another portion integral with said driver transistors operative to pass said given leakage current during said quiescent state.
Claim 11
Dependent Claim
40 words
A memory cell according to claim 9 further including a first pulsed voltage source having a common connection to said driver transistors and second and third voltage sources being connected to one and the other of said driver transistors, respectively.
Claim 12
Dependent Claim
27 words
A memory cell according to claim 11 wherein said portion integral with said transistors and said another portion integral with said driver transistors are back-biased PN junctions.
Claim 13
Dependent Claim
244 words
A memory cell having an active state and a quiescent state comprising: first and second field effect transistors each having source, drain and gate electrodes, said gate electrodes of said first and second transistors being cross-coupled to said drain and said source electrodes connected to a common potential, third and fourth field effect transistors each having source, drain and gate electrodes disposed in series with said first and second field effect transistors, respectively, said drain electrodes of the former being connected to said source electrodes of the latter and said gate electrodes of said third and fourth transistors being interconnected, first and second diodes disposed in series with said first and second field effect transistors, respectively, and in parallel with said third and fourth field effect transistors, respectively, a first pulsed source connected to said gates of said third and fourth field effect transistors, second and third pulse sources connected to said drains of said third and fourth transistors, respectively, said first pulsed source and one of said second and third pulsed sources being actuated to set one of said first and second transistors in the conducting condition, said first pulse source only being actuated to determine which of said first and second transistors is conducting during the active state, and leakage means a portion of which is integral with a portion of each of said transistors said leakage means being operative to provide leakage currents only in said transistors during the quiescent state.
Claim 14
Dependent Claim
37 words
A memory cell according to claim 14 further including amplifier means connected to at least one of said third and fourth field effect transistors to detect the conducting condition of one of said first and second transistors.
Claim 15
Dependent Claim
17 words
A memory cell according to claim 14 wherein said leakage means includes said first and second diodes.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1974-04-05 | 1974-10-05 | 1975-04-06 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1978-04-05 | 1978-10-05 | 1979-04-06 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1982-04-05 | 1982-10-05 | 1983-04-06 | $7700.00 | Window Closed / Lapsed |