Patent US3571628A successfully refreshed from Google Patents.
US3571628A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Pulse circuit
Assignee: AT&T Inc
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Filing: 1968-06-25
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Granted: 1971-03-23
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Expires: 1988-06-25
Abstract
Abstract A pulse timing circuit having an input transistor, a resistorcapacitor timing network, and an output transistor employs an amplifier connected between the timing capacitor and the output transistor to increase the output pulse width. The amplifier current gain increases the allowable value of the timing resistor and the network timing period.
Inventors
- 👤 Edwin J Braun
- 👤 Stanley G Student Jr
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-05 16:27
CPC Classifications
H; H03; H03K; H03K5/00; H03K5/01; H03K5/04
Claims Analysis
Total Claims: 15
Claim 1
Independent Claim
154 words
A pulse generating circuit comprising first and second coupling devices each having input, output and control electrodes, a voltage source, means for applying a signal to said first coupling device control electrode, and pulse timing means coupled between said first coupling device output electrode and said second coupling device control electrode, said timing means comprising a timing capacitor having two terminals, first and second resistors for charging said timing capacitor and an amplifying device having input, output and control electrodes, means for connecting one timing capacitor terminal to said first coupling device output electrode, the other timing capacitor terminal being connected to said amplifying device control electrode, said first charging resistor being connected between the control and output electrodes of said amplifying device, said second charging resistor being connected between said amplifying device output electrode and said voltage source, and said amplifying device input electrode being connected to said second coupling device control electrode.
Claim 2
Dependent Claim
154 words
A pulse generating circuit comprising first and second coupling devices each having input, output and control electrodes, a voltage source, means for applying a signal to said first coupling device control electrode, and pulse timing means coupled between said first coupling device output electrode and said second coupling device control electrode, said timing means comprising a timing capacitor having two terminals, first and second resistors for charging said timing capacitor and an amplifying device having input, output and control electrodes, means for connecting one timing capacitor terminal to said first coupling device output electrode, the other timing capacitor terminal being connected to said amplifying device control electrode, said first charging resistor being connected between the control and output electrodes of said amplifying device, said second charging resistor being connected between said amplifying device output electrode and said voltage source, and said amplifying device input electrode being connected to said second coupling device control electrode.
Claim 3
Dependent Claim
84 words
A pulse generating circuit according to claim 1 further comprising resistor means and a transistor switch having a base, an emitter and a collector, said resistor means being connected between said first coupling means output electrode and said transistor switch base, said transistor switch collector being connected to said second coupling device control electrode and said transistor switch emitter being connected to a reference potential, said transistor switch being operative in response to said signal to delay the operation of said second coupling device.
Claim 4
Dependent Claim
28 words
A pulse generating circuit according to claim 1 further comprising means connected to said one capacitor terminal responsive to the termination of said signal for recharging said capacitor.
Claim 5
Dependent Claim
54 words
A pulse generating circuit according to claim 3 wherein said recharging means comprises a transistor having an emitter, a base and a collector, said transistor base being connected to said input signal applying means, said transistor collector being connected to said voltage source, and said transistor emitter being connected to said one capacitor terminal.
Claim 6
Dependent Claim
41 words
A pulse generating circuit according to claim 4 wherein said connecting means comprises a pair of series-connected like-polarity diodes responsive to said signal for transmitting a selected polarity signal from said first couplIng device output electrode to said one capacitor terminal.
Claim 7
Dependent Claim
147 words
A pulse forming circuit comprising first, second and third transistors each having a base, an emitter and a collector, the second transistor emitter being connected to the third transistor base, a voltage source, means for rendering said first transistor nonconductive an said second and third transistors conductive, timing capacitor means having two terminals means for connecting one of said timing capacitor terminals to the first transistor collector, means for connecting said other timing capacitor terminal to the second transistor base, means for applying an input signal to the first transistor base to render said first transistor conductive and said second and third transistors nonconductive, said means for rendering said second and third transistors conductive comprising first resistive means connected between said voltage source and said second transistor collector and second resistive means connected between the base and collector of said second transistor for charging said timing capacitor.
Claim 8
Dependent Claim
147 words
A pulse forming circuit comprising first, second and third transistors each having a base, an emitter and a collector, the second transistor emitter being connected to the third transistor base, a voltage source, means for rendering said first transistor nonconductive an said second and third transistors conductive, timing capacitor means having two terminals means for connecting one of said timing capacitor terminals to the first transistor collector, means for connecting said other timing capacitor terminal to the second transistor base, means for applying an input signal to the first transistor base to render said first transistor conductive and said second and third transistors nonconductive, said means for rendering said second and third transistors conductive comprising first resistive means connected between said voltage source and said second transistor collector and second resistive means connected between the base and collector of said second transistor for charging said timing capacitor.
Claim 9
Dependent Claim
90 words
A pulse forming circuit according to claim 6 wherein said first and third transistor emitters are connected to a common reference potential, and further comprising means for blocking the conduction of said third transistor during said charging period including a resistor and a fourth transistor having a base, an emitter and a collector, said resistor being connected between said first transistor collector and said fourth transistor base, said fourth transistor collector being connected to said third transistor base and said fourth transistor emitter being connected to said common reference potential.
Claim 10
Dependent Claim
136 words
A pulse forming circuit comprising input and output transistors each having a base, an emitter and a collector, means for applying a pulse to said input transistor base to turn off said input transistor, and means connected between said input transistor collector and said output transistor base responsive to said pulse for controlling said output transistor conduction for a predetermined time, said output transistor conduction controlling means comprising capacitor coupling means, means for connecting said capacitor to said input transistor collector, an amplifying transistor having a base, a collector and an emitter, means for connecting said capacitor to the amplifying transistor base, and a resistor network connected between the base and collector of said amplifying transistor and to a voltage source for charging said capacitor, said amplifying transistor emitter being connected to said output transistor base.
Claim 11
Dependent Claim
136 words
A pulse forming circuit comprising input and output transistors each having a base, an emitter and a collector, means for applying a pulse to said input transistor base to turn off said input transistor, and means connected between said input transistor collector and said output transistor base responsive to said pulse for controlling said output transistor conduction for a predetermined time, said output transistor conduction controlling means comprising capacitor coupling means, means for connecting said capacitor to said input transistor collector, an amplifying transistor having a base, a collector and an emitter, means for connecting said capacitor to the amplifying transistor base, and a resistor network connected between the base and collector of said amplifying transistor and to a voltage source for charging said capacitor, said amplifying transistor emitter being connected to said output transistor base.
Claim 12
Dependent Claim
47 words
A pulse forming circuit according to claim 8 wherein said capacitor coupling means comprises an electrolytic capacitor an said means for connecting said capacitor to said input transistor collector comprises a pair of series-connected diodes, said diodes being operative to limit the reverse polarization of said capacitor.
Claim 13
Dependent Claim
33 words
A pulse forming circuit according to claim 8 characterized in that said output transistor conducts for said predetermined time in response to said applied pulse being of longer duration than said predetermined time.
Claim 14
Dependent Claim
74 words
A pulse forming circuit according to claim 8 further comprising a resistor and a switching transistor having a base, an emitter and a collector, said resistor being connected between said input transistor collector and said switching transistor base, said switching transistor collector being connected to said output transistor base and said switching transistor emitter being connected to said output transistor emitter whereby the conduction of said output transistor is blocked for said predetermined time.
Claim 15
Dependent Claim
33 words
A pulse forming circuit according to claim 8 wherein said output transistor conduction controlling means is operative in response to said applied pulse to turn off said output transistor for said predetermined time.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1974-03-22 | 1974-09-21 | 1975-03-23 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1978-03-22 | 1978-09-21 | 1979-03-23 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1982-03-22 | 1982-09-21 | 1983-03-23 | $7700.00 | Window Closed / Lapsed |