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US3570195A
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US
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Method of forming a recess in a semiconductor substrate having at least one pn junction
Assignee: Toshiba Corp
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Filing: 1968-11-13
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Granted: 1971-03-16
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Expires: 1988-11-13
Abstract
Abstract A METHOD OF FORMING IN A SEMICONDUCTOR SUBSTRATE A RECESS WHOSE DEPTH CAN BE CONTROLLED EXACTLY TO A DESIRED EXTENT, WHICH COMPRISES THE STEPS OF GENERATING A DEPLETION LAYER NEAR AND AT THE PN JUNCTION OF SAID SUBSTRATE, BORING A PART OF SAID SUBSTRATE STARTING WITH THE EXPOSED SURFACE DOWN TO THE DEPLETION LAYER THEREOF SO AS TO CAUSE THE CURRENT FLOWING THROUGH THE PN JUNCTION TO ATTAIN A CERTAIN LEVEL.
Inventors
- 👤 Michio Otsuka
- 👤 Syuji Sugioka
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-05 17:02
CPC Classifications
H; H10; H10P; H10P52/00; H10D; H10D99/00
Claims Analysis
Total Claims: 0
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References Cited (Backward Citations)
No citation records indexed.
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1974-03-15 | 1974-09-14 | 1975-03-16 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1978-03-15 | 1978-09-14 | 1979-03-16 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1982-03-15 | 1982-09-14 | 1983-03-16 | $7700.00 | Window Closed / Lapsed |