Patent US3569953A successfully refreshed from Google Patents.
← Back to Patent Explorer
US3569953A Expired / Lapsed US ⏱️ 0.0 years remaining

Wide range analogue to digital converter

Assignee: GTE Sylvania Inc
•
Filing: 1968-03-25
•
Granted: 1971-03-09
•
Expires: 1988-03-25
📄 Original PDF 🌐 Google Patents 🔄 Sync Now

Abstract

Abstract An analogue to digital converter for logarithmically quantizing an analogue input voltage, which may vary over a wide dynamic range, and providing a representative binary-coded decimal readout. The analogue input voltage is processed through parallel strings of serially connected logarithmic amplifiers, the individual outputs of which are connected to respective threshold detectors at the parallel inputs of a shift register. Upon command, shift pulses are applied to the register to generate a serial output which is applied to a binary counter for readout.

Inventors

  • 👤 Donald G Shuda
  • 👤 Donald L Starkey

Bibliographic Details

Application Number —
Jurisdiction US
Data Source google_patents
Last Synchronized 2026-11-03 15:16
CPC Classifications
H; H03; H03M; H03M1/00; H03M1/06; H03M1/08

Claims Analysis

Total Claims: 10
Claim 1
Independent Claim 138 words
An analogue to digital converter comprising, an analogue signal input terminal, a first string of serially connected amplifiers, the input of the first amplifier in said first string being coupled to said analogue signal input terminal, a plurality of threshold detectors, the outputs of a plurality of the amplifiers in said first string each being coupled to the input of a respective one or more of said threshold detectors, a logic circuit having a plurality of input terminals and a pulse output terminal, the output of each threshold detector being coupled to a respective one of said logic circuit input terminals, and a digital counter connected to the output terminal of said logic circuit and operative in response to output pulses therefrom for producing a digital readout representative of the signal level at said analogue signal input terminal.
Claim 2
Dependent Claim 138 words
An analogue to digital converter comprising, an analogue signal input terminal, a first string of serially connected amplifiers, the input of the first amplifier in said first string being coupled to said analogue signal input terminal, a plurality of threshold detectors, the outputs of a plurality of the amplifiers in said first string each being coupled to the input of a respective one or more of said threshold detectors, a logic circuit having a plurality of input terminals and a pulse output terminal, the output of each threshold detector being coupled to a respective one of said logic circuit input terminals, and a digital counter connected to the output terminal of said logic circuit and operative in response to output pulses therefrom for producing a digital readout representative of the signal level at said analogue signal input terminal.
Claim 3
Dependent Claim 78 words
An analogue to digital converter in accordance with claim 1 wherein each of said first string amplifiers is a logarithmic amplifier, and wherein the number and settings of said threshold detectors and the gain and dynamic range of each of said stRing amplifiers are selected to provide a logarithmic quantization of the signal level applied at said analogue signal input terminal, the digital readout of said counter being representative of said logarithmic quantization of the input signal level.
Claim 4
Dependent Claim 18 words
An analogue to digital converter in accordance with claim 1 wherein said logic circuit comprises a shift register.
Claim 5
Dependent Claim 66 words
An analogue to digital converter in accordance with claim 1 further including a second string of serially connected amplifiers, the input of the first amplifier in said second string being coupled to said analogue signal input terminal, and the outputs of a plurality of the amplifiers in said second string each being coupled to the input of a respective one or more of said threshold detectors.
Claim 6
Dependent Claim 19 words
An analogue to digital converter in accordance with claim 4 wherein wherein said logic circuit comprises a shift register.
Claim 7
Dependent Claim 87 words
An analogue to digital converter in accordance with claim 5 wherein each of the amplifiers in said first and second strings is a logarithmic amplifier, and wherein the number and settings of said threshold detectors and the gain and dynamic range of each of the amplifiers in said first and second strings are selected to provide a logarithmic quantization of the signal level applied at said analogue signal input terminal, the digital readout of said counter being representative of said logarithmic quantization of the input signal level.
Claim 8
Dependent Claim 33 words
An analogue to digital converter in accordance with claim 6 further including means responsive to a command signal for inhibiting the outputs of said threshold detectors and applying shift pulses to said register.
Claim 9
Dependent Claim 135 words
An analogue to digital converter in accordance with claim 7 wherein each of said threshold detectors is operative when triggered to cause a corresponding stage of said shift register to be switched from a quiescent first binary state to a second binary state, each shift pulse applied to the register when its first stage is in the second binary state causes an output pulse to be generated from the register, said register means including an inverter connecting the output of its first stage to the input of its last stage, and said counter is a binary counter operative in response to output pulses from said shift register for producing a binary coded decimal readout which represents the peak signal level at said analogue signal input terminal during the time interval terminated by said command signal.
Claim 10
Dependent Claim 21 words
An analogue to digital converter in accordance with claim 8 wherein each of said threshold detectors comprises a Schmitt trigger circuit.

References Cited (Backward Citations)

US3277463A Cited
US3041469A Cited
US3142056A Cited
US3351930A Cited
US3444550A Cited
US3447147A Cited
US3426296A Cited

USPTO Annuity & Maintenance Windows

Annuity Stage Window Opens Payment Deadline Surcharge Period Until Estimated Fee Status
3.5 Years (Year 4) 1974-03-08 1974-09-07 1975-03-09 $2000.00 Window Closed / Lapsed
7.5 Years (Year 8) 1978-03-08 1978-09-07 1979-03-09 $3760.00 Window Closed / Lapsed
11.5 Years (Year 12) 1982-03-08 1982-09-07 1983-03-09 $7700.00 Window Closed / Lapsed

Assigned Categories & Tags

No categories assigned to this patent yet.

Assign Category Tag