Patent US3567963A successfully refreshed from Google Patents.
US3567963A
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Field effect transistor logic gate
Assignee: United States Department of the Navy
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Filing: 1969-05-22
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Granted: 1971-03-02
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Expires: 1989-05-22
Abstract
Abstract A field effect transistor logic gate having a pair of field effect transistors coupled through their source and drain terminals between information and timing input signals with the source terminal of each field effect transistor coupled to the gate terminal of the other field effect transistor and their drain terminals coupled in common as an output to gate through the information signal in time relation with the timing input signal on their respective source terminals, constituting an AND circuit which AND circuit is readily converted to a half-bit delay circuit by adding a field effect transistor serially in the output and gated by one of the input signals and which half-bits are readily paired and cascaded to 1-bit delay circuits and circulating memory logic circuits.
Inventors
- 👤 Gary A Magee
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-28 12:38
CPC Classifications
G; G11; G11C; G11C19/00; G11C19/18; G11C19/182; G11C19/184; H; H03; H03K; H03K19/00; H03K19/02; H03K19/08; H03K19/094; H03K19/096
Claims Analysis
Total Claims: 8
Claim 1
Independent Claim
122 words
A signal powered field effect transistor logic AND circuit comprising: a first field effect transistor having source, drain, and gate terminals; and a second field effect transistor having source, drain, and gate terminals with the drain terminals of said first and second field effect transistor coupled in common constituting an output and with the source material of each first and second field effect transistor cross coupled to the gate terminal of the other first and second field effect transistor, the source terminal of each first and second field effect transistor constituting a separate input whereby an AND logic circuit is provided for any two voltage signals applied to said two source terminals said voltage signals constituting the supply voltage for circuit operation.
Claim 2
Dependent Claim
122 words
A signal powered field effect transistor logic AND circuit comprising: a first field effect transistor having source, drain, and gate terminals; and a second field effect transistor having source, drain, and gate terminals with the drain terminals of said first and second field effect transistor coupled in common constituting an output and with the source material of each first and second field effect transistor cross coupled to the gate terminal of the other first and second field effect transistor, the source terminal of each first and second field effect transistor constituting a separate input whereby an AND logic circuit is provided for any two voltage signals applied to said two source terminals said voltage signals constituting the supply voltage for circuit operation.
Claim 3
Dependent Claim
26 words
A field effect transistor logic AND circuit as set forth in claim 1 wherein: said first and second field effect transistors are of the N type.
Claim 4
Dependent Claim
26 words
A field effect transistor logic AND circuit as set forth in claim 1 wherein: said first and second field effect transistors are of the P type.
Claim 5
Dependent Claim
126 words
A field effect transistor logic half-bit circuit comprising: a pair of N or P type signal powered field effect transistors each having source, drain, and gate terminals with the drain terminals coupled in common constituting an output and with thE source terminals adapted to be coupled to signal inputs, the source terminal of each field effect transistor being coupled to the gate terminal of the other field effect transistor, constituting an AND logic circuit; and a third N or P type field effect transistor having source, drain, and gate terminals with the source and drain terminals in series in said output and said gate terminal coupled to the source terminal of one of said pair of field effect transistors thereby providing a 1/2 bit delay circuit.
Claim 6
Dependent Claim
126 words
A field effect transistor logic half-bit circuit comprising: a pair of N or P type signal powered field effect transistors each having source, drain, and gate terminals with the drain terminals coupled in common constituting an output and with thE source terminals adapted to be coupled to signal inputs, the source terminal of each field effect transistor being coupled to the gate terminal of the other field effect transistor, constituting an AND logic circuit; and a third N or P type field effect transistor having source, drain, and gate terminals with the source and drain terminals in series in said output and said gate terminal coupled to the source terminal of one of said pair of field effect transistors thereby providing a 1/2 bit delay circuit.
Claim 7
Dependent Claim
212 words
A field effect transistor logic comprising: a pair of N or P type signal powered field effect transistors each having source, drain, and gate terminals with the source terminals of each field effect transistor coupled to the gate terminal of the other field effect transistor, said source terminals constituting signal and first clock timing inputs and said drain terminals coupled in common constituting an output; a third N or P type field effect transistor having source, drain, and gate terminals with the source and drain terminals coupled in series in said output and the gate terminals coupled to the source terminal of one of said pair providing a first 1/2 bit; and a second 1/2 bit consisting of three N or P type field effect transistors constructed and arranged in a circuit identical to said first bit with the output of said first 1/2 bit coupled to one source terminal of one of said field effect transistors in said second 1/2 bit and having a second clock timing input coupled to said other source terminal of the other of said field effect transistors in said second 1/2 bit providing a 1-bit delay logic circuit capable of cascading for a recirculating memory circuit whereby each 1-bit logic circuit provides a 1-bit delay memory.
Claim 8
Dependent Claim
212 words
A field effect transistor logic comprising: a pair of N or P type signal powered field effect transistors each having source, drain, and gate terminals with the source terminals of each field effect transistor coupled to the gate terminal of the other field effect transistor, said source terminals constituting signal and first clock timing inputs and said drain terminals coupled in common constituting an output; a third N or P type field effect transistor having source, drain, and gate terminals with the source and drain terminals coupled in series in said output and the gate terminals coupled to the source terminal of one of said pair providing a first 1/2 bit; and a second 1/2 bit consisting of three N or P type field effect transistors constructed and arranged in a circuit identical to said first bit with the output of said first 1/2 bit coupled to one source terminal of one of said field effect transistors in said second 1/2 bit and having a second clock timing input coupled to said other source terminal of the other of said field effect transistors in said second 1/2 bit providing a 1-bit delay logic circuit capable of cascading for a recirculating memory circuit whereby each 1-bit logic circuit provides a 1-bit delay memory.
References Cited (Backward Citations)
No citation records indexed.
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1974-03-01 | 1974-08-31 | 1975-03-02 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1978-03-01 | 1978-08-31 | 1979-03-02 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1982-03-01 | 1982-08-31 | 1983-03-02 | $7700.00 | Window Closed / Lapsed |