Patent US3566095A successfully refreshed from Google Patents.
US3566095A
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Basic time interval integrator
Assignee: Lockheed Martin Corp
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Filing: 1968-05-22
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Granted: 1971-02-23
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Expires: 1988-05-22
Abstract
Abstract A system for generating timing pulses proportional to the square root of the elapsed number of linear clock pulses employs a reference counter and a linear clock counter, the latter of which counts pulses from a linear clock. A comparator compares the counts in the counters and emits an output pulse when the two counts are the same. In response to successive output pulses from the comparator, the count in the reference counter increases by successive odd numbers and the linear clock counter recounts pulses from the linear clock until its count again equals that in the reference register, so that the successive pulses from the comparator are spaced from their predecessors by a uniformly increasing odd number of linear clock pulses.
Inventors
- 👤 Herbert E Schmitz
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-29 15:01
CPC Classifications
G; G06; G06F; G06F7/00; G06F7/60; G06F7/68; G04; G04F; G04F10/00; G04F10/04
Claims Analysis
Total Claims: 18
Claim 1
Independent Claim
131 words
A signal generator comprising: A. a source of clock signals; B. a first counter coupled to receive and to count said clock signals; C. a second counter having an initial count of one; D. means for comparing the counts in said counters, said comparing means emitting an output signal whenever said counts coincide; and E. means for coupling each said output signal; 1. as a reset signal to said first counter, so that said first counter begins counting anew; and 2. to said second counter so as to increase the count therein by two units, whereby said comparing means emits a train of output signals, each said output signal corresponding to the square root of the number of said clock pulses occurring since the beginning of said train of output signals.
Claim 2
Dependent Claim
131 words
A signal generator comprising: A. a source of clock signals; B. a first counter coupled to receive and to count said clock signals; C. a second counter having an initial count of one; D. means for comparing the counts in said counters, said comparing means emitting an output signal whenever said counts coincide; and E. means for coupling each said output signal; 1. as a reset signal to said first counter, so that said first counter begins counting anew; and 2. to said second counter so as to increase the count therein by two units, whereby said comparing means emits a train of output signals, each said output signal corresponding to the square root of the number of said clock pulses occurring since the beginning of said train of output signals.
Claim 3
Dependent Claim
50 words
to said second counter so as to increase the count therein by two units, whereby said comparing means emits a train of output signals, each said output signal corresponding to the square root of the number of said clock pulses occurring since the beginning of said train of output signals.
Claim 4
Dependent Claim
50 words
to said second counter so as to increase the count therein by two units, whereby said comparing means emits a train of output signals, each said output signal corresponding to the square root of the number of said clock pulses occurring since the beginning of said train of output signals.
Claim 5
Dependent Claim
15 words
A signal generator as defined in claim 1 wherein said clock signals are uniformly spaced.
Claim 6
Dependent Claim
3 words
reset said counters.
Claim 7
Dependent Claim
3 words
reset said counters.
Claim 8
Dependent Claim
52 words
to said second counter so as to increase its count to the next odd number, whereby said comparing means emits a train of output signals, each of said output signals corresponding to the square root of the number of linear clock signaLs elapsed from the beginning of said train of output signals.
Claim 9
Dependent Claim
52 words
to said second counter so as to increase its count to the next odd number, whereby said comparing means emits a train of output signals, each of said output signals corresponding to the square root of the number of linear clock signaLs elapsed from the beginning of said train of output signals.
Claim 10
Dependent Claim
13 words
resetting said counters to ready the system for measuring the next pulse interval.
Claim 11
Dependent Claim
13 words
resetting said counters to ready the system for measuring the next pulse interval.
Claim 12
Dependent Claim
29 words
A signal generator as defined in claim 1 and further including means for simultaneously resetting said first and second counters so as to interrupt said train of output signals.
Claim 13
Dependent Claim
105 words
Apparatus as defined in claim 3 for recording pulse intervals in an input signal, said apparatus further comprising: A. a third counter arranged to count said output signals from said comparing means; B. a memory; C. means for addressing said memory according to the contents of said third counter, and increasing the content of each location in said memory each time that location is addressed; and D. means for detecting the beginning and end of each pulse in said input signal, said detecting means emitting control signals to said addressing means at the beginning and end of each pulse in said input signal so as:
Claim 14
Dependent Claim
77 words
A square count clock comprising: A. a source of linear clock signals; B. a first counter coupled to received and to count said clock signals; C. a second counter arranged to count by two''s from an initial content of one so as to contain only odd numbers; D. means for comparing the counts in said counters, said comprising means emitting an output signal whenever said counts are the same; E. means for coupling each said output signal:
Claim 15
Dependent Claim
77 words
A square count clock comprising: A. a source of linear clock signals; B. a first counter coupled to received and to count said clock signals; C. a second counter arranged to count by two''s from an initial content of one so as to contain only odd numbers; D. means for comparing the counts in said counters, said comprising means emitting an output signal whenever said counts are the same; E. means for coupling each said output signal:
Claim 16
Dependent Claim
23 words
A square count clock as defined in claim 5 and further including means for resetting said counters to interrupt said train of signals.
Claim 17
Dependent Claim
94 words
A clock as defined in claim 6 for measuring pulse intervals in an input signal, said clock further comprising: A. a third counter arranged to count said output signals from said comprising means; B. a memory; C. means for addressing said memory according to the contents of said third counter and increasing the content of each memory location whenever that location is addressed; and D. a detector for detecting the zero axis crossings of said input signal, said detector emitting control signals whenever said input signal crosses said zero axis, each said control signal:
Claim 18
Dependent Claim
22 words
Apparatus as defined in claim 7 and further including a display system for displaying the distribution of counts stored in said memory.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1974-02-22 | 1974-08-24 | 1975-02-23 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1978-02-22 | 1978-08-24 | 1979-02-23 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1982-02-22 | 1982-08-24 | 1983-02-23 | $7700.00 | Window Closed / Lapsed |