Patent US3566023A successfully refreshed from Google Patents.
US3566023A
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Sequential dot, digitally encoded television system
Assignee: TDK Micronas GmbH
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Filing: 1967-08-03
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Granted: 1971-02-23
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Expires: 1987-08-03
Abstract
Abstract A sequential dot, digitally encoded, raster-type television system including an input circuit for receiving a time-based video signal having recurrent line and frame synchronizing signals; a clock pulse generator is provided for generating a train of clock pulses having a frequency
Inventors
- 👤 Edward S Smierciak
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-02 22:18
CPC Classifications
H; H04; H04N; H04N7/00; H04N7/12; H04N7/122; H04N7/125; H04N3/00; H04N3/10; H04N3/30
Claims Analysis
Total Claims: 9
Claim 1
Independent Claim
244 words
A sequential dot, digitally encoded, raster-type television transmission system comprising: input circuit means for receiving a time-based video signal having recurrent line and frame synchronizing signals; sequential dot video output circuit means; means for generating a train of rEcurrent sampling signals having a frequency where fv is the frequency of said frame synchronizing signals, L is the number of lines in one frame, D is a predetermined number of picture elements in one line, n1 is the vertical interlace ratio and n2 is a predetermined dot interlace ratio, the quotient LD/n1n2 being irreducible; means for generating a train of recurrent timing signals having a frequency fc fen2; means for actuating said timing signal generating means in response to each said line synchronizing signal thereby to initiate a said train of timing signals; and means for terminating each said train of timing signals in response to D timing signals; fc being such that each interval between successive line synchronizing signals is longer than D timing signals; said sampling signal generating means being responsive to said timing signals; means for coupling said input circuit means to said output circuit means in response to said train of sampling signals thereby to pass analogue video signals from said input circuit means to said output circuit means; means for detecting the amplitudes of said sampled video signals and for providing signals respectively responsive to a plurality of predetermined amplitude levels thereof; and means for digitally encoding said last-named signals.
Claim 2
Dependent Claim
244 words
A sequential dot, digitally encoded, raster-type television transmission system comprising: input circuit means for receiving a time-based video signal having recurrent line and frame synchronizing signals; sequential dot video output circuit means; means for generating a train of rEcurrent sampling signals having a frequency where fv is the frequency of said frame synchronizing signals, L is the number of lines in one frame, D is a predetermined number of picture elements in one line, n1 is the vertical interlace ratio and n2 is a predetermined dot interlace ratio, the quotient LD/n1n2 being irreducible; means for generating a train of recurrent timing signals having a frequency fc fen2; means for actuating said timing signal generating means in response to each said line synchronizing signal thereby to initiate a said train of timing signals; and means for terminating each said train of timing signals in response to D timing signals; fc being such that each interval between successive line synchronizing signals is longer than D timing signals; said sampling signal generating means being responsive to said timing signals; means for coupling said input circuit means to said output circuit means in response to said train of sampling signals thereby to pass analogue video signals from said input circuit means to said output circuit means; means for detecting the amplitudes of said sampled video signals and for providing signals respectively responsive to a plurality of predetermined amplitude levels thereof; and means for digitally encoding said last-named signals.
Claim 3
Dependent Claim
36 words
The system of claim 1 wherein said encoding means includes means for converting said last-named signals to parallel binary coded signal form, and means for converting said parallel binary coded signals to serial binary coded form.
Claim 4
Dependent Claim
31 words
The system of claim 1 wherein said detecting means includes means for comparing the amplitudes of said sampled video signals in a plurality of reference signals respectively having said predetermined levels.
Claim 5
Dependent Claim
21 words
The system of claim 2 wherein said last-named converting means includes shift register means responsive to said timing signal generating means.
Claim 6
Dependent Claim
31 words
The system of claim 1 further comprising transmission means coupled to said encoding means; video signal monitor means; and digital-to-analogue signal converting means coupling said transmission means to said monitor means.
Claim 7
Dependent Claim
58 words
The system of claim 2 further comprising transmission means coupled to said parallel-to-series converting means; video signal monitor means; means coupled to said transmission means for converting said serial binary coded signals to parallel binary coded form; and means coupling said last-named converting means to said monitor means for converting said parallel binary coded signals to analogue form.
Claim 8
Dependent Claim
50 words
The system of claim 5 further comprising means for generating a second train of sampling signals having a frequency fe; means for synchronizing said first and second-named generating means; and means for coupling said digital-to-analogue converting means to said monitor means in response to said second train of sampling signals.
Claim 9
Dependent Claim
217 words
The system of claim 1 wherein said coupling means includes means for coupling said line and frame synchronizing signals to said output circuit means; and further comprising means for transmitting said digitally encoded signals and said line and frame synchronizing signals; video signal monitor means having video signal input circuit means and line and frame sweep means; means coupling said transmitting means to said line and frame sweep means for separating said line and frame sweep signals; digital-to-analogue signal converting means coupled to said transmitting means for converting said encoded digital signals to corresponding analogue signals; second means for generating a second train of recurrent timing signals having a frequency fc, means coupling said separating means to said second generating means for actuating the same in response to each separated line synchronizing signal thereby to initiate said second train of timing signals; means for terminating each said second train of timing Signals in response to D second timing signals; second means for generating a second train of sampling signals having a frequency fe, said second sampling signal generating means being coupled to said second timing signal generating means and actuated thereby; and means coupling said digital-to-analogue signal converting means to said input circuit means of said monitor means in response to said second train of sampling signals.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1974-02-22 | 1974-08-24 | 1975-02-23 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1978-02-22 | 1978-08-24 | 1979-02-23 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1982-02-22 | 1982-08-24 | 1983-02-23 | $7700.00 | Window Closed / Lapsed |