Asynchronous interface for use between a main memory and a central processing unit

Abstract

Abstract AN ASYNCHRONOUS INTERFACE WHICH SELECTIVELY INTERRUPTS THE CLOCK PULSES APPLIED TO A CENTRAL PROCESSING UNIT THEREBY PERMITTING A HIGH SPEED CENTRAL PROCESSING UNIT (CPU) TO OPERATE WITH A LOW SPEED MAIN MEMORY HAVING A RELATIVELY LONG CYCLE TIME OR WITH A PLURALITY OF MAIN MEMORIES HAVING DIFFERENT CYCLE TIMES. THE OPERATION OF THE CPU IS CONTROLLED BY CLOCK PULSES. WHEN THE CPU SELECTS A MAIN MEMORY AND REQUESTS DATA CAN BE PROCESSED, ADDRESS IN THE EMEMORY SO THAT THE DATA CAN BE PROCESSED, A BUSY SIGNAL IS GENERATED FOR A PREDETERMINED FOLLOWING PORTION OF THE SELECTED MEMORY CYCLE. THE BUSY SIGNAL INTERRUPTS THE CLOCK PULSES SO THAT ANOTHER SELECTION OF THE MEMORY CANNOT BE MADE UNTIL THE MEMORY IS READY TO ACCEPT THE ADDRESS OF THE DATA TO BE USED IN THE NEXT REQUEST AT WHICH TIME THE CLOCK PULSES ARE AGAIN APPLIED TO THE CPU. SINCE THE ACCESS TIME OF THE MEMORY MAY BE SO LONG THAT THE REQUESTED DATA IS NOT AVAILABLE AT THE MEMORY OUTPUT WHEN THE CPU IS READY TO ACCEPT AND PROCESS THE DATA, THE CLOCK PULSES ARE INTERRUPTED FOR A PREDETERMINED TIME UNTIL THE DATA IS AVAILABLE, AT WHICH TIME AN ADVANCE SIGNAL IS GENERATED BY THE MEMORY TO INDICATE THE DATA WILL BE AVAILABLE THE NEXT TIME THE CPU IS ABLE TO ACCEPT THIS DATA. BY THE USE OF MEMEORYGENERATED BUSY AND ADVANCE SIGNALS TO INTERRUPT THE CPU CLOCK PUSES, A HIGH SPEED CPU MAY BE USED WITH MEMORIES HAVING DIFFERENT CYCLE TIMES AND DIFFERENT ACCESS TIMES WITHOUT THE NEED FOR CHANGING THE CONTROL LOGIC IN THE CPU.

Inventors

• 👤 Raymond W Faivre
• 👤 Donald E Waldecker

Bibliographic Details