Patent US3564286A successfully refreshed from Google Patents.
US3564286A
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Solid state voltage matcher and voltage difference detector for use therein
Assignee: Westinghouse Electric Corp
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Filing: 1968-01-02
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Granted: 1971-02-16
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Expires: 1988-01-02
Abstract
Abstract Two direct current difference voltages, of opposite polarity, are obtained, one by subtracting a voltage corresponding to the bus from a voltage corresponding to the generator, and the other by subtracting a voltage corresponding to the generator from a voltage corresponding to the bus, and are applied to the bases of separate transistors both of which, together with a third transistor, comprise a two-input-level detector. If the bus voltage is greater than the generator voltage by an amount which is greater than an adjustable threshold level established by varying the setting of a potentiometer arm connected to the base of the third transistor, an output is applied to a first AND circuit. If the generator voltage is greater than the bus voltage by an amount which is greater than the threshold level, an output is applied to a second AND circuit. A timer connected to both AND circuits supplies a pulse of adjustable width and predetermined repetition rate to both AND circuits simultaneously; the AND circuit which has an additional input thereto in accordance with the relative magnitudes of the bus and generator voltages supplies a pulse signal to an output transistor which energizes a relay winding. The two output transistors supplied from the two AND circuits respectively energize relay windings to supply ''''raise volts'''' and ''''lower volts'''' pulses to a motor-driven voltage-adjusting rheostat operatively connected to the generator.
Inventors
- 👤 Tibor Rubner
- 👤 John H Bednarek
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-28 16:19
CPC Classifications
H; H02; H02J; H02J3/00; H02J3/38; H02J3/40; H02J3/42; H03; H03K; H03K5/00; H03K5/22; H03K5/24
Claims Analysis
Total Claims: 9
Claim 1
Independent Claim
144 words
In voltage-matching apparatus, in combination, means for obtaining two difference voltages of opposite polarities representing respectively a first voltage minus a second voltage and the second voltage minus the first voltage, level detector means operatively connected to the means for obtaining two difference voltages, said level detector means utilizing the difference voltages for selectively producing a first output when said first voltage exceeds the second voltage by at least a predetermined amount and selectively producing a second output when said second voltage exceeds said first voltage by at least said predetermined amount, a first AND circuit having said first output applied thereto as one input, a second AND circuit having said second output applied thereto as one input, and timer pulse producing means operatively connected to both the first and second AND Circuits and simultaneously supplying a second input to both said AND circuits.
Claim 2
Dependent Claim
144 words
In voltage-matching apparatus, in combination, means for obtaining two difference voltages of opposite polarities representing respectively a first voltage minus a second voltage and the second voltage minus the first voltage, level detector means operatively connected to the means for obtaining two difference voltages, said level detector means utilizing the difference voltages for selectively producing a first output when said first voltage exceeds the second voltage by at least a predetermined amount and selectively producing a second output when said second voltage exceeds said first voltage by at least said predetermined amount, a first AND circuit having said first output applied thereto as one input, a second AND circuit having said second output applied thereto as one input, and timer pulse producing means operatively connected to both the first and second AND Circuits and simultaneously supplying a second input to both said AND circuits.
Claim 3
Dependent Claim
67 words
Apparatus according to claim 1 including in addition first and sEcond output pulse-producing means connected to the first and second AND circuits respectively for producing ''''raise voltage'''' and ''''lower voltage'''' control signals respectively while the first and second outputs of the level detector means are selectively applied to the first and second AND circuits coincidentally with the application thereto of pulses from the timer pulse producing means.
Claim 4
Dependent Claim
90 words
Apparatus according to claim 1 in which the timer pulse-producing means includes a circuit portion having a capacitor therein chargeable in predetermined times through two circuit paths, charging the capacitor through one path controlling the pulse repetition rate, charging the capacitor through the other path controlling the pulse width, the timer pulse-producing means including an additional circuit portion having therein a triggered bistable device operatively connected to said capacitor, the triggered bistable device in one state selecting one charging path and in the other state selecting the other charging path.
Claim 5
Dependent Claim
43 words
Apparatus according to claim 1 in which the means for obtaining two difference voltages includes two transformers each having two secondary windings, and a plurality of rectifier and filter means for separately obtaining a direct current signal from each of the secondary windings.
Claim 6
Dependent Claim
198 words
In voltage matching apparatus, in combination, means for obtaining two equal difference voltages of opposite polarities representing respectively a first voltage minus a second voltage and the second voltage minus the first voltage, a two-input-level detector circuit means including three transistors, the circuit means including means for adjusting the voltage on the vase of one transistor to establish a selected voltage accuracy limit whereby the level detector circuit means produces an output only when the difference voltage is greater than a selected permissible voltage, first output circuit means and second output circuit means both operatively connected to the two-input-level detector circuit means, the two-input-level detector circuit means being constructed and arranged to utilize the two difference voltages to selectively produce a first output and supply said first output to the first output circuit means when said first voltage exceeds the second voltage by at least a predetermined amount and one which is greater than the permissible voltage and to selectively produce a second output and supply said second output to said second output circuit means when said second voltage exceeds the first voltage by at least a predetermined amount and one which is greater than the permissible voltage.
Claim 7
Dependent Claim
198 words
In voltage matching apparatus, in combination, means for obtaining two equal difference voltages of opposite polarities representing respectively a first voltage minus a second voltage and the second voltage minus the first voltage, a two-input-level detector circuit means including three transistors, the circuit means including means for adjusting the voltage on the vase of one transistor to establish a selected voltage accuracy limit whereby the level detector circuit means produces an output only when the difference voltage is greater than a selected permissible voltage, first output circuit means and second output circuit means both operatively connected to the two-input-level detector circuit means, the two-input-level detector circuit means being constructed and arranged to utilize the two difference voltages to selectively produce a first output and supply said first output to the first output circuit means when said first voltage exceeds the second voltage by at least a predetermined amount and one which is greater than the permissible voltage and to selectively produce a second output and supply said second output to said second output circuit means when said second voltage exceeds the first voltage by at least a predetermined amount and one which is greater than the permissible voltage.
Claim 8
Dependent Claim
229 words
Apparatus according to claim 5 in which the first voltage corresponds to the voltage on an energized bus and the second voltage corresponds to the voltage of a generator to corresponds connected to the bus when the difference between the first and second voltages is within permissible limits as defined by said selected voltage accuracy limit, wherein the first output circuit means includes an AND circuit having the first output of the level detector circuit means applied thereto as one input, wherein the second output circuit means includes and additional AND circuit having the second output of the level detector circuit means applied thereto as one input, a pulse generator having means for adjusting the duration of the pulses generated therein and a predetermined wait time between pulses operatively connected to the AND circuit and to the additional AND circuit and supplying the pulses generated therein to both AND circuits simultaneously as a second input to both AND circuits, said AND circuit producing an output control signal when the first output of the level detector circuit means is applied thereto coincident with the application thereto of a pulse from the pulse generator means, said additional AND circuit producing an additional output control signal when the second output of the level detector circuit means is applied thereto coincident with the apPlication thereto of a pulse from the pulse generator means.
Claim 9
Dependent Claim
123 words
Apparatus according to claim 6 including in addition fourth and fifth transistors, first and second relays, and circuit means interconnecting the fourth and fifth transistors and the first and second relays, the last-named circuit means being adapted to be connected to a source of energizing potential for the fourth and fifth transistors and being constructed and arranged whereby selective operation of the relays insure that the source of potential is connected at any time to only one fourth and fifth transistors, the last-named circuit means connecting the fourth and fifth transistors to the AND circuit and to the additional AND circuit whereby the output control signal and the additional output control signal are applied as inputs to the fourth and fifth transistors respectively.
References Cited (Backward Citations)
US2454807A
Cited
US3328599A
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1974-02-15 | 1974-08-17 | 1975-02-16 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1978-02-15 | 1978-08-17 | 1979-02-16 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1982-02-15 | 1982-08-17 | 1983-02-16 | $7700.00 | Window Closed / Lapsed |