US3564226A — Parallel binary processing system having minimal …

Claim 1

Independent Claim 256 words

Digital data processing apparatus comprising: A. digital arithmetic means (20); 1. having first and second input ports (20a, 20b) and an output port (20c); 2. for developing at said output port electrical signals that are a selected arithmetic function of electrical signals applied to said first and second input ports; B. a plurality of digital registers (28, 30, 32, 34, 36) arranged in first and second groups, each of said groups comprising at least one register; C. first and second gating means (40, 42) 1. respectively in circuit between said first group of registers and said first input port of said arithmetic means and between said second group of registers and said second input port of said arithmetic means; 2. each of said first and second gating means being operative in response to control signals applied thereto to transfer electrical signals identifying digital information in any register connected therewith to said arithmetic means; D. third gating means (44, 46) 1. in circuit between said output port of said arithmetic means and said first and second groups of registers; 2. operative in response to control signals applied thereto to apply the signals from said output (from) port of said arithmetic means to one of said registers; and E. control means (38) coupled to said first, second and third gating means and Adapted to be responsive to a selected set of instruction-identifying signals for simultaneously applying to said gating means all control signals in a selected set of control signals in response to the set of instructionidentifying signals.

Claim 2

Dependent Claim 256 words

Digital data processing apparatus comprising: A. digital arithmetic means (20); 1. having first and second input ports (20a, 20b) and an output port (20c); 2. for developing at said output port electrical signals that are a selected arithmetic function of electrical signals applied to said first and second input ports; B. a plurality of digital registers (28, 30, 32, 34, 36) arranged in first and second groups, each of said groups comprising at least one register; C. first and second gating means (40, 42) 1. respectively in circuit between said first group of registers and said first input port of said arithmetic means and between said second group of registers and said second input port of said arithmetic means; 2. each of said first and second gating means being operative in response to control signals applied thereto to transfer electrical signals identifying digital information in any register connected therewith to said arithmetic means; D. third gating means (44, 46) 1. in circuit between said output port of said arithmetic means and said first and second groups of registers; 2. operative in response to control signals applied thereto to apply the signals from said output (from) port of said arithmetic means to one of said registers; and E. control means (38) coupled to said first, second and third gating means and Adapted to be responsive to a selected set of instruction-identifying signals for simultaneously applying to said gating means all control signals in a selected set of control signals in response to the set of instructionidentifying signals.

Claim 3

Dependent Claim 40 words

for producing in response to different input signals different combinations of substantially simultaneous control signals to provide a signal path at least from the inputs to one of said first and second groups of gates to said adder output port.

Claim 4

Dependent Claim 40 words

for producing in response to different input signals different combinations of substantially simultaneous control signals to provide a signal path at least from the inputs to one of said first and second groups of gates to said adder output port.

Claim 5

Dependent Claim 24 words

automatically producing at said output port digital signals identifying the logical sum of the digital numbers identified by signals applied to said input ports;

Claim 6

Dependent Claim 24 words

automatically producing at said output port digital signals identifying the logical sum of the digital numbers identified by signals applied to said input ports;

Claim 7

Dependent Claim 31 words

operative in response to control signals to apply output signals from each of said second and third registers in parallel to said first adder input port; E. second coincidence gates (42):

Claim 8

Dependent Claim 31 words

operative in response to control signals to apply output signals from each of said second and third registers in parallel to said first adder input port; E. second coincidence gates (42):

Claim 9

Dependent Claim 29 words

operative in response to control signals to apply output signals from said memory buffer register in parallel to said second adder input port; F. third coincidence gates (44, 46)

Claim 10

Dependent Claim 29 words

operative in response to control signals to apply output signals from said memory buffer register in parallel to said second adder input port; F. third coincidence gates (44, 46)

Claim 11

Dependent Claim 44 words

operative in response to control signals to apply the digital information output from said adder in parallel to any of said three registers; and G. control means (30) for generating all of the control signals for said first, second and third coincidence gates simultaneously.

Claim 12

Dependent Claim 44 words

operative in response to control signals to apply the digital information output from said adder in parallel to any of said three registers; and G. control means (30) for generating all of the control signals for said first, second and third coincidence gates simultaneously.

Claim 13

Dependent Claim 111 words

including means responsive to selected control signals from said control means for applying a second level signal to each B bus conductor when an associated conductor of said A bus carries said second level signal; G. a multiple-conductor O 0-bus (48); H. a group of register gates (46) coupled to said O bus and to said registers for transferring digital signals from said O bus to any one of said registers; and I. a group of O bus gates (44) connected between said adder output port and said O bus for transferring to each O bus conductor the output signal from any one of a plurality of stages of said adder.

Claim 14

Dependent Claim 111 words

including means responsive to selected control signals from said control means for applying a second level signal to each B bus conductor when an associated conductor of said A bus carries said second level signal; G. a multiple-conductor O 0-bus (48); H. a group of register gates (46) coupled to said O bus and to said registers for transferring digital signals from said O bus to any one of said registers; and I. a group of O bus gates (44) connected between said adder output port and said O bus for transferring to each O bus conductor the output signal from any one of a plurality of stages of said adder.

Claim 15

Dependent Claim 133 words

producing at said output port the logical sum of the digital signals applied to said input ports without appreciable delay after receipt thereof, B. a multiple-conductor A bus (22) connected to said first adder input port; C. a multiple-conductor B bus (24) connected to said second adder input port; each conductor of said A bus being associated with one conductor of said B bus; D. first, second, third and fourth digital registers (28, 30, 32, 34, 36) having substantially zero delay; E. a first group of coincidence gates (40) coupled to said first, second and third registers and said A bus to transfer digital signals stored in each of said first, second and third registers to said A bus in response to selected control signals; F. a second group of coincidence gates (42)

Claim 16

Dependent Claim 133 words

producing at said output port the logical sum of the digital signals applied to said input ports without appreciable delay after receipt thereof, B. a multiple-conductor A bus (22) connected to said first adder input port; C. a multiple-conductor B bus (24) connected to said second adder input port; each conductor of said A bus being associated with one conductor of said B bus; D. first, second, third and fourth digital registers (28, 30, 32, 34, 36) having substantially zero delay; E. a first group of coincidence gates (40) coupled to said first, second and third registers and said A bus to transfer digital signals stored in each of said first, second and third registers to said A bus in response to selected control signals; F. a second group of coincidence gates (42)

Claim 17

Dependent Claim 15 words

for producing selected combinations of control signals in response to the signals applied thereto; and

Claim 18

Dependent Claim 15 words

for producing selected combinations of control signals in response to the signals applied thereto; and

Claim 19

Dependent Claim 59 words

for developing at said output port electrical signals that are a selected arithmetic function of electrical signals applied to said first and second input ports; B. a plurality of digital registers (28, 30, 32, 34, 36) arranged in first and second groups, each of said groups comprising at least one register; C. first and second gating means (40, 42)

Claim 20

Dependent Claim 59 words

for developing at said output port electrical signals that are a selected arithmetic function of electrical signals applied to said first and second input ports; B. a plurality of digital registers (28, 30, 32, 34, 36) arranged in first and second groups, each of said groups comprising at least one register; C. first and second gating means (40, 42)

Claim 21

Dependent Claim 39 words

each of said first and second gating means being operative in response to control signals applied thereto to transfer electrical signals identifying digital information in any register connected therewith to said arithmetic means; D. third gating means (44, 46)

Claim 22

Dependent Claim 39 words

each of said first and second gating means being operative in response to control signals applied thereto to transfer electrical signals identifying digital information in any register connected therewith to said arithmetic means; D. third gating means (44, 46)

Claim 23

Dependent Claim 77 words

operative in response to control signals applied thereto to apply the signals from said output (from) port of said arithmetic means to one of said registers; and E. control means (38) coupled to said first, second and third gating means and Adapted to be responsive to a selected set of instruction-identifying signals for simultaneously applying to said gating means all control signals in a selected set of control signals in response to the set of instruction-identifying signals.

Claim 24

Dependent Claim 77 words

operative in response to control signals applied thereto to apply the signals from said output (from) port of said arithmetic means to one of said registers; and E. control means (38) coupled to said first, second and third gating means and Adapted to be responsive to a selected set of instruction-identifying signals for simultaneously applying to said gating means all control signals in a selected set of control signals in response to the set of instruction-identifying signals.

Claim 25

Dependent Claim 45 words

Apparatus according to claim 1 wherein each said register has essentially zero delay between the receipt of an input signal from said third gating means and the application of a signal responsive to said input signal to one of said first and second gating means.

Claim 26

Dependent Claim 83 words

has a plurality of input conductors (22) at said first input port and a like plurality of conductors (24) at said second input port, each conductor at said first input port being associated with one conductor at said second input port; and B. said second gating means (42) are adapted for applying to each conductor at said second adder input port a first digital signal only when said first digital signal is absent from the associated conductor at said first adder input port.

Claim 27

Dependent Claim 83 words

has a plurality of input conductors (22) at said first input port and a like plurality of conductors (24) at said second input port, each conductor at said first input port being associated with one conductor at said second input port; and B. said second gating means (42) are adapted for applying to each conductor at said second adder input port a first digital signal only when said first digital signal is absent from the associated conductor at said first adder input port.

Claim 28

Dependent Claim 26 words

coupled to said second gating means (42) to apply information output from said memory element to said arithmetic means by way of said second gating means.

Claim 29

Dependent Claim 26 words

coupled to said second gating means (42) to apply information output from said memory element to said arithmetic means by way of said second gating means.

Claim 30

Dependent Claim 24 words

for producing at mutually overlapping times all the control signals developed in response to the input signals applied thereto at substantially the same time.

Claim 31

Dependent Claim 24 words

for producing at mutually overlapping times all the control signals developed in response to the input signals applied thereto at substantially the same time.

Claim 32

Dependent Claim 31 words

Apparatus according to claim 2 wherein said control means produces all said control signals developed in response to a set of input signals thereto at mutually coincident and simultaneously terminating times.

Claim 33

Dependent Claim 50 words

producing said sum signals without appreciable deLay after receipt of said input signals; B. a substantially zero-delay memory buffer register (36) having input terminals and output terminals; C. at least second and third substantially zero-delay registers (28, 30), each having input terminals and output terminals; D. first coincidence gates (40)

Claim 34

Dependent Claim 50 words

producing said sum signals without appreciable deLay after receipt of said input signals; B. a substantially zero-delay memory buffer register (36) having input terminals and output terminals; C. at least second and third substantially zero-delay registers (28, 30), each having input terminals and output terminals; D. first coincidence gates (40)

Claim 35

Dependent Claim 17 words

Apparatus according to claim 1 wherein said control means generates said control signals as direct voltage levels.

Claim 36

Dependent Claim 44 words

Apparatus according to claim 1 wherein said second gating means (42) further comprise means for applying to said second input port of said arithmetic means a selected function of the electrical signals applied to said first input port in response to said control means.

Claim 37

Dependent Claim 11 words

Apparatus according to claim 1 wherein: A. said arithmetic means (20)

Claim 38

Dependent Claim 53 words

Apparatus according to claim 1 further comprising an input-output element (14): A. coupled to said third gating means (44, 46) to apply signals from said input-output element to said registers by way of said third gating means; and B. coupled to said arithmetic means to receive signals only from said output port thereof.

Claim 39

Dependent Claim 12 words

Apparatus according to claim 1: A. further comprising a memory element (10)

Claim 40

Dependent Claim 89 words

Digital data processing apparatus according to claim 1 in which: A. said arithmetic means is a parallel digital adder; B. each of said first, second and third gating means is coupled to said digital adder for transferring signals between the one or more registers connected therewith and said adder in parallel; and C. said adder and each of said registers and each of said gating means operates with essentially zero delay between the receipt of input signals and the production of output signals in response to said input signals.

Claim 41

Dependent Claim 53 words

Apparatus according to claim 1 wherein said control means is further arranged to: A. respond to said instruction-identifying signals to identify the information transfers required to perform the instruction said signals identify; and B. apply enabling signals to said gating means to provide the signal paths required for said identified information transfers simultaneously.

Claim 42

Dependent Claim 19 words

A digital processor element arranged to process multiple-digit words, said processor element comprising: A. a parallel digital adder (20)

Claim 43

Dependent Claim 19 words

A digital processor element arranged to process multiple-digit words, said processor element comprising: A. a parallel digital adder (20)

Claim 44

Dependent Claim 13 words

A processing element according to claim 11 wherein said control means (30) is:

Claim 45

Dependent Claim 24 words

A processor element for processing multiple-digit works in a digital data processing system, said processing element comprising: A. a parallel multiple-stage digital adder (20a)

Claim 46

Dependent Claim 24 words

A processor element for processing multiple-digit works in a digital data processing system, said processing element comprising: A. a parallel multiple-stage digital adder (20a)

Claim 47

Dependent Claim 14 words

A processor element according to claim 13: A. fUrther comprising a control unit (38)

Annuity Stage	Window Opens	Payment Deadline	Surcharge Period Until	Estimated Fee	Status
3.5 Years (Year 4)	1974-02-15	1974-08-17	1975-02-16	$2000.00	Window Closed / Lapsed
7.5 Years (Year 8)	1978-02-15	1978-08-17	1979-02-16	$3760.00	Window Closed / Lapsed
11.5 Years (Year 12)	1982-02-15	1982-08-17	1983-02-16	$7700.00	Window Closed / Lapsed

Parallel binary processing system having minimal operational delay

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