Patent US3560810A successfully refreshed from Google Patents.
US3560810A
Expired / Lapsed
US
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Field effect transistor having passivated gate insulator
Assignee: International Business Machines Corp
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Filing: 1968-08-15
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Granted: 1971-02-02
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Expires: 1988-08-15
Abstract
Abstract An insulated-gate field effect transistor is described which includes a gate insulator defined as a laminate structure comprising a phosphosilicate glass (PSG) layer and a silicon dioxide (SiO2) layer, the ratio of the thicknesses of such layers and, also, the P2O5 concentration in the PSG layer being properly chosen to insure stable device characteristics over extended periods under operation conditions.
Inventors
- 👤 Pieter Balk
- 👤 David W Dong
- 👤 Jerome M Eldrige
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-28 19:40
CPC Classifications
H; H10; H10D; H10D64/00; H10D64/60; H10D64/66; H10D64/68; H10D64/681; H10D99/00; H10P; H10P14/00; H10P14/60; H10P14/69; H10P14/692; H10P14/6921; H10P14/69215; H10P14/6922; H10P14/6923
Claims Analysis
Total Claims: 11
Claim 1
Independent Claim
163 words
An insulated-gate field effect transistor comprising: a semiconductor body of first conductivity type having a major planar surface and spaced source and drain diffusions of second conductivity type formed in said surface, portions of said surface intermediate said source and drain diffusions defining a conduction channel; a thin layer of dielectric material formed over at least said surface portions defining said conduction channel; a gate electrode formed over said thin dielectric layers in field-applying relationship with said surface portions defining said conduction channel; and the improvement comprising a thin layer of phosphosilicate glass included in said thin dielectric layer and extending in a plane substantially parallel to and noncontiguous with said surface portions defining said conduction channel, said glass layer having a mole fraction of P205 of less than 0.09 and wherein the ratio of the thickness x g of said glass layer to the thickness x o of said dielectric layer intermediate said glass layer and said surface does not exceed 3.
Claim 2
Dependent Claim
18 words
A field effect transistor as defined in claim 2 wherein said body is formed of n -type silicon.
Claim 3
Dependent Claim
19 words
An insulated-gate field effect transistor as defined in claim 2 wherein said body is formed of p -type silicon.
Claim 4
Dependent Claim
20 words
An insulated-gate field effect transistor as defined in claim 2 wherein said thin dielectric layer is formed of silicon dioxide.
Claim 5
Dependent Claim
23 words
An insulated-gate field effect transistor as defined in claim 2 wherein said glass layer has a P205 concentration less than 6 mole percent.
Claim 6
Dependent Claim
39 words
An insulated-gate field effect transistor as defined in claim 2 wherein the ratio of thickness x g of said glass layer to the thickness x0of said dielectric layer intermediate said glass layer and said surface does not exceed 1.
Claim 7
Dependent Claim
23 words
An insulated-gate field effect transistor as defined in claim 2 wherein the mole fraction of P205 in said glass layer is greater than
Claim 8
Dependent Claim
58 words
An insulated-gate field effect transistor as defined in claim 2 wherein the ratio of the thickness x g of said glass layer to the thickness x o of said dielectric layer intermediate said glass layer and said surface portion is less than 1 and the mole fraction of P2 05 in said glass layer is between and 0.09
Claim 9
Dependent Claim
56 words
An insulated-gate field effect transistor as defined in claim 2 wherein the ratio of the thickness x g of said glass layer to the thickness x o of said dielectRic layer intermediate said glass layer and said surface is less than 1 and the mole fraction of P205 in said glass layer is between and 0.06.
Claim 10
Dependent Claim
24 words
An insulated-gate field effect transistor as defined in claim 2 wherein the mole fraction of P205 in said glass layer is between and 0.06.
Claim 11
Dependent Claim
34 words
An insulated-gate field effect transistor as defined in claim 2 wherein the combined thickness of said glass layer and said dielectric layer intermediate said glass layer and said surface is between 200 and 1,000A.
References Cited (Backward Citations)
US3334281A
Cited
US3476619A
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1974-02-01 | 1974-08-03 | 1975-02-02 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1978-02-01 | 1978-08-03 | 1979-02-02 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1982-02-01 | 1982-08-03 | 1983-02-02 | $7700.00 | Window Closed / Lapsed |