High speed logic element

Claim 2

A flip-flop circuit comprising, a pair of output transistors: first and second multiemitTer transistor means for receiving set and reset signals connected to the inputs of said output transistors; capacitive means cross-coupled between the outputs of said output transistors and their inputs, said connection causing regenerative feedback to be applied to the output transistors on opposite sides of the circuit; means for biasing said first, second and output transistors; and bilateral triggering means connected to the biasing means for said first and second transistors and to the inputs of said output transistors so that, upon application of an appropriate trigger, the output transistor which is off is driven on and the biasing of the on transistor is altered so as to drive said transistor off, said actions occurring simultaneously and effecting a simultaneous change of state of said output transistors.

Claim 3

A flip-flop circuit as described in claim 1 wherein said bilateral triggering means comprises: a third and fourth multiemitter transistor; means for applying input signals to said third and fourth transistors and including means for simultaneous application of a clock pulse to each transistor emitter input; fifth and sixth transistor means having their outputs cross-coupled to the inputs to said output transistors and having their collectors connected to said first and second transistors and biasing means so as to create a unidirectional flow of current away from one side of the circuit and to the other side, depending upon the state of the circuit and the bias level of the transistors.

Claim 4

A JK flip-flop circuit comprising: a pair of output transistors whose collector output determines the state of the flip-flop and whose emitters are grounded; a first pair of multiemitter transistors having their collector outputs connected to the bases of said output transistors via a diode and grounded resistor, and having one emitter DC connected to the output transistor collector on the opposite side of said multiemitter transistor; a voltage source and output resistor in series with the collectors of said output transistors; a pair of capacitors each connected between the collector of one output transistor and the base of the opposing output transistor; a pair of emitter follower transistors having their collectors connected between the bases of said first pair of multiemitter transistors and their associated voltage source and resistor and having their emitters cross-coupled to the bases of the output transistor on the opposite side of the circuit; a second pair of multiemitter transistors having their collector outputs connected to the bases of said emitter follower transistors and having two emitters connected to logic inputs and a third emitter commonly connected to a clock pulse; and a voltage source and current limiting resistor in series with the bases of said first and second pair of multiemitter transistors.

Claim 5

A JK flip-flop circuit comprising: a pair of output transistors whose collector output determines the state of the flip-flop and whose emitters are grounded; a first pair of multiemitter transistors having their collector outputs connected to the bases of said output transistors via a diode and grounded resistor, and having one emitter DC connected to the output transistor collector on the opposite side of said multiemitter transistor; a voltage source and output resistor in series with the collectors of said output transistors; a pair of capacitors each connected between the collector of one output transistor and the base of the opposing output transistor; a pair of emitter follower transistors having their collectors connected between the bases of said first pair of multiemitter transistors and their associated voltage source and resistor and having their emitters cross-coupled to the bases of the output transistor on the opposite side of the circuit; a second pair of multiemitter transistors having their collector outputs connected to the bases of said emitter follower transistors and having two emitters connected to logic inputs and a third emitter commonly connected to a clock pulse; and a voltage source and current limiting resistor in series with the bases of said first and second pair of multiemitter transistors.

Claim 6

A flip-flop circuit according to claim 3 wherein the components comprising said circuit are formed in a semiconductor body comprising: a plurality of first regions of high impurity concentration N + or - type of semiconductivity in PN junction forming relation with the surface of a high resistivity P-type semiconducting substrate; an epitaxial layer of N-type of semiconductivity extending over the surface of said substrate and first regions, said layer also acting as a transistor collector region; a plurality of second regions of P-type of semiconductivity in PN junction forming relation with said epitaxial layer; a plurality of second regions of P + or - type of semiconductivity extending through said epitaxial region to contact the remaining first region, whereby capacitors are formed; third regions of N + or - type conductivity in PN junction forming relation with at least a portion of said second regions over said first and second regions whereby said first, second and third regions and the portions of the epitaxial layer between said first and sEcond regions cooperate to form a plurality of transistors having a collector (first region), a base (second region) and an emitter (third region) or plurality of emitters; a plurality of high impurity concentration P + or - type second regions of semiconductivity diffused through said epitaxial layer so as to form electrical isolation areas surrounding components of said circuit; a plurality of said third regions of N + or - type of conductivity diffused across the junction formed by said capacitor forming second region of P-type conductivity and abutting epitaxial layer; a plurality of said third regions of N + or - type of conductivity diffused into said epitaxial layer so as to form electrical contact areas to transistor collector regions; a plurality of regions of P-type of semiconductivity in PN junction forming relation with said epitaxial layer forming a plurality of resistors thereby; terminal means for supplying an input signal to those transistors having multiple emitters and terminal means for removing an output signal from the collectors of the output transistors; means for electrically interconnecting said transistors, diodes, capacitors and resistors.

Claim 7

A flip-flop circuit according to claim 4 wherein the resistivity of said second regions of capacitor forming P + or - type of semiconductivity is increased or decreased to yield like changes in capacitance values, said resistivity changes being effected without altering other parts of the circuit.