High speed mos read-only memory

Claim 2

A sense-amplifier means for an MOS memory apparatus comprising: input terminal means and output terminal means, said input terminal means being adapted for connection to the output of an MOS memory apparatus, said output terminal means being adapted for connection to a data utilization apparatus; first potential supply means and second potential supply means; first FET means having its source connected to said input terminal means and its drain connected to said first potential supply means; second FET means having its drain connected to said input terminal means and its source connected to said second potential supply means, said first and second FET means being biased to cause said input terminal means to normally assume a predetermined quiescent potential; and bistable circuit means connected between said input terminal means and said output terminal means, said bistable circuit means being biased so as to provide an output of one state when the potential of said input terminal means is at said quiescent potential and to provide an output of another state in response to a change in potential at said input terminal means.

Claim 3

A sense-amplifier means for an MOS memory apparatus as recited in claim 1 and further including reference potential supply means for providing a reference potential different from said quiescent potential, said bistable circuit means including a differential amplifier means comprised of a third FET means and a fourth FET means connected in parallel between said first potential supply means and said second potential supply means, the gate of said third FET means being connected to said input terminal means so as to bias said third FET means normally ON in response to said quiescent potential, said fourth FET means having its gate connected to said reference potential supply means for biasing said fourth FET means normally OFF.

Claim 4

A sense-amplifier means for an MOS memory apparatus as recited in claim 2 wherein said reference potential supply means includes a fifth FET means and a sixth FET means, said reference potential being obtained from the drain of said fifth FET means the source of which is connected to said second potential supply means and the drain of which is connected through said sixth FET means to said first potential supply means.

Claim 5

A sense-amplifier means for an MOS memory apparatus as recited in claim 3 wherein a seventh FET means is provided for use as a current source for said differential amplifier means, said seventh FET means having its source connected to said second potential supply means, its drain connected to the sources of said third and fourth FET means, and its gate connected to said reference potential supply means.

Claim 6

A sense-amplifier means for an MOS memory apparatus as recited in claim 4 wherein said differential amplifier means further includes an eighth FET means having its source connected to the drain of said fourth FET means and its drain connected to said first potential supply means, said eighth FET means serving as A load means across which the output of said sense-amplifier means is taken.

Claim 7

A sense-amplifier means for an MOS memory apparatus as recited in claim 5 and further including another amplifying stage comprised of a ninth FET means, the drain of said ninth FET means being connected to said output terminal means.

Claim 8

An integrated MOS memory and sense-amplifier apparatus formed of a plurality of MOS FET devices disposed on a single chip of semiconductive material, said apparatus comprising: first potential supply means and second potential supply means; common terminal means and a plurality of address terminals; a plurality of storage FETs having their sources connected to said first potential supply means and their drains connected to said common terminal means, the gates of said storage FETs being individually connected to ones of said address terminals; first and second FET means, said common terminal means being connected to the source of said first FET means, the drain of said first FET means being connected to said second potential supply means, said common terminal means being also connected to the drain of said second FET means the source of which is connected to said first potential supply means; and bistable circuit means having an input connected to said common terminal means, said bistable circuit means being biased to operate in one state when no address signal is applied to any of said address terminals and to switch to another state when an address signal is applied to one of said address terminals.

Claim 9

An integrated MOS memory and sense-amplifier apparatus formed of a plurality of MOS FET devices disposed on a single chip of semiconductive material, said apparatus comprising: first potential supply means and second potential supply means; common terminal means and a plurality of address terminals; a plurality of storage FETs having their sources connected to said first potential supply means and their drains connected to said common terminal means, the gates of said storage FETs being individually connected to ones of said address terminals; first and second FET means, said common terminal means being connected to the source of said first FET means, the drain of said first FET means being connected to said second potential supply means, said common terminal means being also connected to the drain of said second FET means the source of which is connected to said first potential supply means; and bistable circuit means having an input connected to said common terminal means, said bistable circuit means being biased to operate in one state when no address signal is applied to any of said address terminals and to switch to another state when an address signal is applied to one of said address terminals.

Claim 10

An integrated MOS memory and sense-amplifier apparatus as recited in claim 7 wherein said bistable circuit means includes a reference potential supply means and a differential amplifier means comprised of a third FET means and a fourth FET means connected in parallel between said first potential supply means and said second potential supply means, the gate of said third FET means being connected to said common terminal means, said third FET means being biased normally ON but the quiescent potential at said common terminal means, said fourth FET means having its gate connected to said reference potential supply means, said reference potential supply means having a potential different from the quiescent potential at said common terminal means for biasing said fourth FET means normally OFF.

Claim 11

An integrated MOS memory and sense-amplifier apparatus as recited in claim 8 wherein said reference potential supply means includes a fifth and a sixth FET means, the reference potential being obtained from the drain of said fifth FET means the source of which is connected to said first potential supply means and the drain of which is connected through said sixth FET means to said second potential supply means.

Claim 12

An integrated MOS memory and sense-amplifier apparatus as recited in claim 9 wherein a seventh FET means is provided for use as a current source for said differential amplifier means, said seventh FET means having its source connected to said first potential supply means, its drain connected to the sources of said third and fourth FET means, and its gage connected to said reference potential supply means.

Claim 13

An integrated MOS memory and sense-amplifier apparatus as recited in claim 10 wherein said differential amplifier means further includes an eighth FET means having its source connected to the drain of said fourth FET means and its drain connected to said second potential supply means, said eighth FET means serving as a load means across which the output of said differential amplifier means is taken.

Claim 14

An integrated MOS and sense-amplifier apparatus as recited in claim 11 and further including another amplifying stage comprised of a ninth FET means and a tenth FET means serially connected together between said second potential supply means and said first potential supply means, the output of said differential amplifier means being connected to the gAte of said ninth FET means, the output of said sense-amplifier apparatus being taken from the drain of said ninth FET means.