US3560760A
Expired / Lapsed
US
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Logic nand gate circuits
Assignee: Texas Instruments Inc
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Filing: 1970-02-02
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Granted: 1971-02-02
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Expires: 1990-02-02
Abstract
Abstract Disclosed are logic NAND gate circuits of the type capable of driving a low impedance or a high capacitance load while maintaining relatively fast propagation speed which include a pair of output transistors of one type respectively connected to bias voltage supplies and connected in common to an output circuit, and a plurality of input transistors connected between the bases of the output transistors. A logic 1 input signal at any one of the input transistors produces a logic 0 output signal.
Inventors
- 👤 David H Chung
- 👤 Bill H Terrell
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-01 10:44
CPC Classifications
H; H03; H03K; H03K19/00; H03K19/02; H03K19/08; H03K19/082; H03K19/086
Claims Analysis
Total Claims: 18
Claim 1
Independent Claim
218 words
A logic gate circuit of the type capable of driving a low impedance or a high capacitive load while maintaining relatively fast propagation speed, comprising in combination: a. first and second output transistors of the same type wherein the emitter of said first output transistor is electrically common with the collector of said second output transistor and form the output of said logic gate circuit; and b. at least one input transistor in which: 1. the collector is common with the base of said first output transistor, 2. the emitter is common with the base of said second output transistor, and 3. the base forms a logic input for the logic gate circuit; and wherein c. the collector of the first output transistor is connected to a collector supply voltage terminal; and wherein d. the collector of each input transistor is connected to said collector supply voltage terminal through a resistance; and wherein e. the emitter of each input transistor is connected to said collector supply voltage terminal and to an emitter supply voltage terminal through respective resistances; and wherein f. the emitter of said second output transistor is connected to said emitter voltage supply terminal through a resistance; whereby g. said collector and emitter voltage supplies bias said transistors such that each operates in a nonsaturated mode.
Claim 2
Dependent Claim
218 words
A logic gate circuit of the type capable of driving a low impedance or a high capacitive load while maintaining relatively fast propagation speed, comprising in combination: a. first and second output transistors of the same type wherein the emitter of said first output transistor is electrically common with the collector of said second output transistor and form the output of said logic gate circuit; and b. at least one input transistor in which: 1. the collector is common with the base of said first output transistor, 2. the emitter is common with the base of said second output transistor, and 3. the base forms a logic input for the logic gate circuit; and wherein c. the collector of the first output transistor is connected to a collector supply voltage terminal; and wherein d. the collector of each input transistor is connected to said collector supply voltage terminal through a resistance; and wherein e. the emitter of each input transistor is connected to said collector supply voltage terminal and to an emitter supply voltage terminal through respective resistances; and wherein f. the emitter of said second output transistor is connected to said emitter voltage supply terminal through a resistance; whereby g. said collector and emitter voltage supplies bias said transistors such that each operates in a nonsaturated mode.
Claim 3
Dependent Claim
13 words
the emitter is common with the base of said second output transistor, and
Claim 4
Dependent Claim
13 words
the emitter is common with the base of said second output transistor, and
Claim 5
Dependent Claim
108 words
The logic gate circuit of claim 1 wherein: a. at least two of said logic gate circuits are combined to have their output circuits connected in common to a system output circuit so as to form a composite logic gate circuit; whereby b. when a logic 0 input signal is applied to all of said input transistors of said logic gate circuits, a logic 1 output signal is produced in said system output circuit, and when a logic 1 input signal is simultaneously applied to any one input transistor of each of said logic gate circuits, a logic 0 output signal is produced in said system output circuit.
Claim 6
Dependent Claim
14 words
the collector of said first output transistor is connected to said collector voltage supply;
Claim 7
Dependent Claim
14 words
the collector of said first output transistor is connected to said collector voltage supply;
Claim 8
Dependent Claim
15 words
The logic gate circuit of claim 1 wherein at least three input transistors are provided.
Claim 9
Dependent Claim
116 words
the base forms a logic input for the logic gate circuit; and wherein c. the collector of the first output transistor is connected to a collector supply voltage terminal; and wherein d. the collector of each input transistor is connected to said collector supply voltage terminal through a resistance; and wherein e. the emitter of each input transistor is connected to said collector supply voltage terminal and to an emitter supply voltage terminal through respective resistances; and wherein f. the emitter of said second output transistor is connected to said emitter voltage supply terminal through a resistance; whereby g. said collector and emitter voltage supplies bias said transistors such that each operates in a nonsaturated mode.
Claim 10
Dependent Claim
116 words
the base forms a logic input for the logic gate circuit; and wherein c. the collector of the first output transistor is connected to a collector supply voltage terminal; and wherein d. the collector of each input transistor is connected to said collector supply voltage terminal through a resistance; and wherein e. the emitter of each input transistor is connected to said collector supply voltage terminal and to an emitter supply voltage terminal through respective resistances; and wherein f. the emitter of said second output transistor is connected to said emitter voltage supply terminal through a resistance; whereby g. said collector and emitter voltage supplies bias said transistors such that each operates in a nonsaturated mode.
Claim 11
Dependent Claim
18 words
the emitter of said second transistor is connected to said first emitter voltage supply through a resistance; and
Claim 12
Dependent Claim
18 words
the emitter of said second transistor is connected to said first emitter voltage supply through a resistance; and
Claim 13
Dependent Claim
64 words
A logic NAND gate circuit of the type capable of driving a low impedance or a high capacitive load while maintaining relatively fast propagation speed, comprising in combination: a. a collector voltage supply, first and second emitter voltage supplies, and a third voltage supply; b. a plurality of input circuits and an output circuit; c. first and second output transistors of one type wherein:
Claim 14
Dependent Claim
64 words
A logic NAND gate circuit of the type capable of driving a low impedance or a high capacitive load while maintaining relatively fast propagation speed, comprising in combination: a. a collector voltage supply, first and second emitter voltage supplies, and a third voltage supply; b. a plurality of input circuits and an output circuit; c. first and second output transistors of one type wherein:
Claim 15
Dependent Claim
172 words
the bases of said first and second transistors are respectively connected to said collector and second emitter voltage supplies through respective resistances; d. said output circuit is connected to said third voltage supply; and e. a plurality of input transistors of said one type each having its collector connected to the base of said first transistor, its emitter connected to the base of said second transistor, and its base connected to a respective input circuit; wherein f. said third voltage supply has a value between said collector voltage supply and said emitter voltage supplies, and said collector, first and second emitter, and said third voltage supplies are preselected so that said first, second and input transistors are operating in the nonsaturated mode; and wherein g. the bases of said input transistors form a logic input for said NAND gate circuit, whereby when a logic 1 input signal is applied to any one of said input transistors through its respective input circuit, a logic 0 output signal is produced in said output circuit.
Claim 16
Dependent Claim
172 words
the bases of said first and second transistors are respectively connected to said collector and second emitter voltage supplies through respective resistances; d. said output circuit is connected to said third voltage supply; and e. a plurality of input transistors of said one type each having its collector connected to the base of said first transistor, its emitter connected to the base of said second transistor, and its base connected to a respective input circuit; wherein f. said third voltage supply has a value between said collector voltage supply and said emitter voltage supplies, and said collector, first and second emitter, and said third voltage supplies are preselected so that said first, second and input transistors are operating in the nonsaturated mode; and wherein g. the bases of said input transistors form a logic input for said NAND gate circuit, whereby when a logic 1 input signal is applied to any one of said input transistors through its respective input circuit, a logic 0 output signal is produced in said output circuit.
Claim 17
Dependent Claim
113 words
The logic NAND gate circuit of claim 4 wherein: a. at least two of said NAND gate circuits are combined to have their output circuits connected in common to a system output circuits connected in common to a system output circuit so as to form a composite NAND gate circuit; whereby b. when a logic 1 input signal is applied to any one of said input transistors of one of said NAND gate circuits, and at the same time a logic 1 input signal is applied to any one of said input transistors of the other of said NAND gate circuits, a logic 0 output signal is produced in said system output circuit.
Claim 18
Dependent Claim
15 words
The logic gate circuit of claim 4 wherein at least three input transistors are provided.
References Cited (Backward Citations)
US3136901A
Cited
US3229119A
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1974-02-01 | 1974-08-03 | 1975-02-02 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1978-02-01 | 1978-08-03 | 1979-02-02 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1982-02-01 | 1982-08-03 | 1983-02-02 | $7700.00 | Window Closed / Lapsed |