Automatic electronic counter apparatus

Claim 2

Counter apparatus having, in combination, a signal processor for producing impulses the signal periods of which are to be measured, a source of clock pulses, gating means connected with said source and said signal processor, respectively, and each having output circuit means, a pair of counting registers connected with said output circuit means, respectively, one to accumulate counts of said clock pulses and a second to count signal periods during a measurement time, programming means connected with the gating means for controlling the commencement and duration of the measurement time, monitoring means connected with both counting registers for determining when the count in the said one register has reached any one of several predetermined numbers less than the complete full count thereof and dependent upon the concurrent count in said second register, means for connecting the monitoring means with the programming means to cause the programming means to effect the termination of the said measurement time in response to the said determining, and means connected to said registers for dividing the count of the said one register into that of the said second register to provide a measure of the frequency corresponding to the said signal periods.

Claim 3

Apparatus as claim in claim 1 and in which the said counting registers are decimal and the said monitoring means comprises gate control logic circuit means having means for receiving the most significant digit count of the said one register and the least significant digit count of the said second register and in which the programming means has means to produce a stop signal for application to the gating means upon the advent of the next pulse from the said signal processor after the said determining.

Claim 4

Counter apparatus having, in combination, a signal processor which produces one pulse for each cycle of the signal, the periods of which are to be measured, said pulses having a uniform time relation to the zero crossing of said signal, a source of clock pulses, gating means connected with said source and said signal processor, respectively, and each having output circuit means, a pair of counting registers connected with said output circuit means, respectively, one to accumulate counts of said clock pulses and a second to count signal periods during a measurement time, programming means connected with the gating means for controlling the commencement and duration of the measurement time, monitoring means connected with both counting registers for determining when the count in said one register has reached any one of several predetermined numbers less than the complete full count thereof, and dependent upon the concurrent count in said second register, means for connecting the monitoring means with the programming means to cause the programming means to effect the termination of the said measurement time in response to the said determining, and means connected to said registers for dividing the count of the said one regIster into that of the said second register to provide a measure of the frequency corresponding to the said signal periods.

Claim 5

Counter apparatus having, in combination, a signal processor which produces one pulse for each cycle of the signal, the periods of which are to be measured, said pulses having a uniform time relation to the zero crossing of said signal, a source of clock pulses, gating means connected with said source and said signal processor, respectively, and each having output circuit means, a pair of counting registers connected with said output circuit means, respectively, one to accumulate counts of said clock pulses and a second to count signal periods during a measurement time, programming means connected with the gating means for controlling the commencement and duration of the measurement time, monitoring means connected with both counting registers for determining when the count in said one register has reached any one of several predetermined numbers less than the complete full count thereof, and dependent upon the concurrent count in said second register, means for connecting the monitoring means with the programming means to cause the programming means to effect the termination of the said measurement time in response to the said determining, and means connected to said registers for dividing the count of the said one regIster into that of the said second register to provide a measure of the frequency corresponding to the said signal periods.

Claim 6

Apparatus as claim in claim 3 and in which the said counting registers are decimal and the said monitoring means comprises gate control logic circuit means having means for receiving the two most significant digits of the said one register and the last significant digit of the said second register and in which the said programming means has means to produce a stop signal for application to the gating means upon the advent of the next pulse from the said signal processor after the said determining.

Claim 7

Apparatus as claimed in claim 3 and in which the said counting registers are binary and the said monitoring means comprises gate control logic circuit means having means for receiving the second through the sixth most significant bits of the said one register and the two least significant bits of the said second register and in which the said programming means has means to produce a stop signal for application to the gating means upon the advent of the next pulse from a said signal processor after the said determining.