Patent US3553369A successfully refreshed from Google Patents.
US3553369A
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US
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Supervision circuit for synchronization transmitters
Assignee: Siemens AG
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Filing: 1968-01-23
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Granted: 1971-01-05
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Expires: 1988-01-23
Abstract
Abstract A circuit to supervise synchronization transmitters to determine if they are functioning properly, and if not, to substitute therefor correctly operating synchronization transmitters. A transistor arrangement is provided to obtain criteria indicative of the operating condition of the synchronization transmitters. A plurality of synchronization transmitters may be supervised to determine the operating conditions thereof with a single supervision circuit. Asynchronous operation of the transmitters is also indicated by the supervision circuit.
Inventors
- 👤 Walter Flohrer
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-02 13:50
CPC Classifications
H; H04; H04L; H04L7/00; H04L7/0079; H04L7/0083
Claims Analysis
Total Claims: 9
Claim 1
Independent Claim
272 words
A circuit to supervise first (TG11) and second (TG21) synchronization transmitters normally functioning to produce synchronous first (TA1) and second (TA2) synchronizing signals, respectively, comprising: first switching means (G1, I; T4, T5, T1) connected to the outputs of the first and second synchronization transmitters, the switching state thereof being controlled in response to signals applied thereto by the first and second synchronization transmitters to produce first and second indicating signals corresponding to the operating states of the first and second synchronization transmitters, respectively; second (G2, T3) and third (G3, T2) switching means connected to the first switching means to receive the first and second indicating signals, respectively; first (S1) and second (S2) indicating means connected to the second (G2, T3) and third (G3, T2) switching means, respectively, the second switching means (G2, T3) being responsive to the first indicating signals produced by the first switching means in response to nonfunctioning of the second synchronization transmitter (TG21) to cause activation of the first indicating means (S1) to produce an indication thereof; the third switching means (G3, T2) being responsive to the second indicating signals produced by the first switching means in response to nonfunctioning of the first synchronization transmitter (TG11) to cause activation of the second indicating means (S2) to produce an indication thereof; the second (G2, T3) and third (G3, T2) switching means being alternately responsive to the first and second indicating signals, respectively, produced by the first switching means when the first (TG11) and second (TG21) synchronization transmitters are functioning asychronously to cause corresponding alternate activation of the second (S2) and first (S1) indicating means, respectively to produce an indication thereof.
Claim 2
Dependent Claim
272 words
A circuit to supervise first (TG11) and second (TG21) synchronization transmitters normally functioning to produce synchronous first (TA1) and second (TA2) synchronizing signals, respectively, comprising: first switching means (G1, I; T4, T5, T1) connected to the outputs of the first and second synchronization transmitters, the switching state thereof being controlled in response to signals applied thereto by the first and second synchronization transmitters to produce first and second indicating signals corresponding to the operating states of the first and second synchronization transmitters, respectively; second (G2, T3) and third (G3, T2) switching means connected to the first switching means to receive the first and second indicating signals, respectively; first (S1) and second (S2) indicating means connected to the second (G2, T3) and third (G3, T2) switching means, respectively, the second switching means (G2, T3) being responsive to the first indicating signals produced by the first switching means in response to nonfunctioning of the second synchronization transmitter (TG21) to cause activation of the first indicating means (S1) to produce an indication thereof; the third switching means (G3, T2) being responsive to the second indicating signals produced by the first switching means in response to nonfunctioning of the first synchronization transmitter (TG11) to cause activation of the second indicating means (S2) to produce an indication thereof; the second (G2, T3) and third (G3, T2) switching means being alternately responsive to the first and second indicating signals, respectively, produced by the first switching means when the first (TG11) and second (TG21) synchronization transmitters are functioning asychronously to cause corresponding alternate activation of the second (S2) and first (S1) indicating means, respectively to produce an indication thereof.
Claim 3
Dependent Claim
162 words
The circuit recited in claim 1 wherein the fIrst switching means comprise first (T4) and second (T5) transistors having inputs connected to the outputs of the first (TG11) and second (TG21) synchronization transmitters, respectively, and a third transistor (T1) having its input connected to the outputs of the first (T4) and second (T5) transistors; the second and third switching means comprising fourth (T3) and fifth (T2) transistors, respectively, having inputs connected to the outputs of the first (T4) and third (T1), and second (T5) and third (T1), transistors, respectively; biasing means (G3-G7, R6-R8) connected to the circuit to cause the first (T4) and second (T5) transistor to selectively control conduction of the fourth (T3) and fifth (T2) transistors, respectively, when the first (TG11) and second (TG21) synchronization transmitters are not functioning normally, and to cause the third transistor (T1) to control conduction of the fourth (T3) and fifth (T2) transistors when the first (TG11) and second (TG21) synchronization transmitters are functioning normally.
Claim 4
Dependent Claim
72 words
The circuit recited in claim 2 further comprising first (C1, R2) and second (C1'', R2'') resistive-capacitive means interposed between the first (TG11) and second (TG21) synchronization transmitters and the first (T1) and second (T2) transmitters, respectively, having time constants corresponding to the time duration of the first and second synchronizing signals to enable the latter to control conduction of the first (T1) and second (T2) transistors, respectively, during the time duration thereof.
Claim 5
Dependent Claim
57 words
The circuit recited in claim 3 further comprising a plurality of first and second synchronization transmitters that form first (TG11-TG1n) and second (TG21-TG2n) groups of synchronization transmitters, the first (C1, R2) and second (C1'', R2'') resistive-capacitive means being interposed between the fist and second groups of synchronization transmitters and the first (TG11) and second (TG21) transistors, respectively.
Claim 6
Dependent Claim
39 words
The circuit recited in claim 4 further comprising a plurality of first (D1-D4) and second (D1''-D4'') -D4'') decoupling means interposed between each of the plurality of first and second synchronization transmitters and the first and second resistive-capacitive means, respectively.
Claim 7
Dependent Claim
111 words
The circuit recited in claim 5 further comprising: additional resistive-capacitive means connected between additional first and second synchronization transmitters comprising the first and second groups of transmitters that produce synchronizing signals of time duration that is a whole number multiple of the time duration of the first and second synchronizing signals produced by the other synchronization transmitters comprising the same group and the first and second transistors, respectively, the time constant of the additional resistive-capacitive means corresponding to the time duration of the synchronizing signals of the additional first and second synchronization transmitters to enable control of conduction of the first and second transistors for the time duration of the latter.
Claim 8
Dependent Claim
41 words
The circuit recited in claim 3 wherein the first (C1, R2) and second (C1'', R2'') resistive-capacitive means are interposed between the first (TG11) and second (TG21) synchronization transmitters and the base circuits of the first (T1) and second (T2) transistors, respectively.
Claim 9
Dependent Claim
41 words
The circuit recited in claim 6 wherein the first (C1, R2) and second (C1'', R2'') resistive-capacitive means are interposed between the first (TG11) and second (TG21) synchronization transmitters and the base circuits of the first (T1) and second (T2) transistors, respectively.
References Cited (Backward Citations)
US3161732A
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1974-01-04 | 1974-07-06 | 1975-01-05 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1978-01-04 | 1978-07-06 | 1979-01-05 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1982-01-04 | 1982-07-06 | 1983-01-05 | $7700.00 | Window Closed / Lapsed |