Electrical communications systems

Claim 1

A SWITCHING STAGE FOR A T.D.M. DIGITAL COMMUNICATIONS SYSTEM, INCLDING A LOCAL MASTER TIMING OSCILLATOR OPERABLE TO DETERMINE AT LEAST LOCAL CHANNEL TIME SLOT AND LOCAL DIGIT TIMES OF SAID STAGE, SAID OSCILLATOR HAVING A FREQUENCY CONTROL INPUT, THE FREQUENCY OF SAID OSCILATOR BEING ADJUSTABLE BY SIGNALS APPLIED TO SAID CONTROL INPUT, AT LEAST ONE TWO-WAY COMMUNICATION LINK CONNECTED TO SAID STAGE, THE SAID STAGE HAVING FOR EACH SAID COMMUNICATION LINK CONNECTED TO IT, SEPARATE DIGIT STORAGE MEANS OPERABLY CONTROLLED BY SAID MASTER TIMING OSCILLATOR AND DIGITS INCOMING TO THE STAGE ON SAID COMMUNICATION LINK TEMPORARILY TO STORE SAID INCOMING DIGITS THEREBY TO ABSORB DIFFERENCES BETWEEN INCOMING DIGIT TIMES AND CORRESPONDING LOCAL DIGIT TIMES, SENSING MEANS OPERABLY RESPONSIVE TO THE STATE OR FILL OF SAID STORAGE MEANS TO GENERATE FIRST D.C. ERROR SIGNALS HAVING A SIGN AND MAGNITUDE DEPENDENT ON THE SAID STATE OF FILL OF THE STORAGE MEANS, MEANS OPERABLE TO ENCODE SAID FIRST ERROR SIGNALS AND TO TRANSMIT SAID ENCODED SIGNALS TO SAID COMMUNICATION LINK IN SELECTED OUTGOINING CHANNEL SLOTS, MEANS OPERABLE TO RECEIVE ENCODED FIRST D.C. ERROR SIGNALS FROM SELECTED INCOMING CHANNEL SLOTS ON SAID COMMUNICATION LINK AND TO CONVERT SAID RECEIVED ENCODED SIGNALS INTO SECOND D.C. ERROR SIGNALS HAVING OPPOSITE POLARITY TO THE D.C. ERROR SIGNALS FROM WHICH THEY ORIGINATE AND MEANS CONNECTED TO ADD ALGEBRAICALLY THE FIRST AND SECOND D.C. ERROR SIGNALS TO PRODUCE A COMPOSITE ERROR SIGNAL AND TO APPLY SAID COMPOSITE ERROR SIGNAL TO SAID FREQUENCY CONTROL INPUT OF THE MASTER OSCILLATOR IN SUCH A SENSE TO CHANGE THE FREQUENCY OF SAID OSCILLATOR THAT THE SAID COMPOSITE D.C. ERROR SIGNAL IS REDUCED.