Gated dc coupled j-k flip-flop

Claim 1

A DC COUPLED J-K FLIP-FLOP INCLUSING IN COMBINATION: (A) A SLAVE BISTABLE FLIP-FLOP PORTION HAVING AN INTERNAL BISTABLE SWITCHING ELEMENT AND FIRST AND SECOND INPUTS COUPLED THERETO FOR RECEIVING BINARY LOGIC INFORMATION CAPABLE OF CHANGING THE CONDUCTIVE STATE OF THE FLIP-FLOP, SAID SLAVE FLIP-FLOP PORTION FURTHER INCLUDING FIRST AND SECOND CONTROL TERMINALS WHICH ALTERNATELY EXIST AT HIGH AND LOW LOGICAL LEVELS DEPENDING UPON THE CONDUCTIVE STATE OF THE FLIP-FLOP, (B) A MASTER BISTABLE FLIP-FLOP PORTION HAVING AN INTERNAL BISTABLE SWITCHING ELEMENT AND FIRST AND SECOND INPUT TERMINALS COUPLED THERETO, SAID FIRST NAMED FIRST AND SECOND INPUT TERMINALS ALSO CONNECTED RESPECTIVELY TO THE FIRST AND SECOND CONTROL TERMINALS OF THE SLAVE PORTION OF THE FLIP-FLOP FOR RECEIVING THEREFROM BINARY LOGIC INFORMATION FOR CONTROLLING THE CONDUCTIVE STATE OF THE MASTER BISTABLE FLIP-FLOP PORTION, SAID MASTER BISTABLE FLIP-FLOP PORTION FURTHER HAVING FIRST AND SECOND OUTPUT TERMINALS WHICH ARE CONNECTED RESPECTIVELY TO SAID FIRST AND SECOND INPUT TERMINALS OF THE SLAVE PORTION OF THE FLIP-FLOP AND WHICH EXIST ALTERNATELY AT HIGH AND LOW LOGICAL LEVELS DEPENDING UPON THE CONDUCTIVE STATE OF THE MASTER PORTION OF THE FLIP-FLOP, AND (C) CLOCKING MEANS COUPLED TO THE INTERNAL BISTABLE SWITCHING ELEMENTS OF THE SLAVE AND MASTER FLIP-FLOP PORTIONS AND CONNECTABLE TO A SOURCE OF CLOCK SIGNALS FOR HOLDING SAID MASTER PORTION OF THE FLIP-FLOP IN A FIXED CONDUCTIVE STATE AND FOR ENABLING THE CONDUCTIVE STATE OF THE SLAVE PORTION OF THE FLIP-FLOP TO BE FREELY CHANGED BY BINARY SIGNALS APPLIED THERETO WHEN CLOCK SIGNALS ARE AT A FIRST PREDETERMINED LOGICAL LEVEL, SAID CLOCKING MEANS ENABLING THE BINARY LOGIC LEVELS AT THE FIRST AND SECOND CONTROL TERMINALS OF THE SLAVE PORTION OF THE FLIP-FLOP TO CONTROL THE CONDUCTIVE STATE OF THE MASTER PORTION OF THE FLIP-FLOP ONLY WHEN CLOCK