Gated storage elements for a semiconductor memory

Claim 1

AN INPUT GATING CIRCUIT FOR A BISTABLE MEMEORY CIRCUIT, THE MEMORY CIRCUIT INCLUDING FIRST AND SECOND CURRENT SWITCHING MEANS COUPLED IN A BISTABLE CIRCUIT CONFIGURATION AND OPERATIVE TO ALTERNATELY CONDUCT AS THE MEMORY CIRCUIT IS SWITCHED FROM ONE TO THE OTHER OF ITS TWO BISTABLE STATES, THE INPUT GATING CIRCUIT ADAPTED TO BE CONNECTED TO THE OUTPUT TERMINALS OF A PRIOR MEMORY STAGE AND DIFFERENTIALLY DRIVEN THEREBY, SAID INPUT GATING CIRCUIT INCLUDING, IN COMBINATION: A FIRST PRESET GATE COUPLED IN PARALLEL WITH SAID FIRST CURRENT SWITCHING MEANS AND A SECOND PRESET GATE COUPLED IN PARALLEL WITH SAID SECOND CURRENT SWITCHING MEANS, THE FIRST AND SECOND PRESET GATES CONNECTED TO A FIRST COMMON NODE AND THE FIRST AND SECOND CURRENT SWITCHING MEANS CONNECTED TO A SECOND COMMON NODE, A CURRENT SWITHCING REFERENCE GATE DIFFERENTIALLY CONNECTED TO A CURRENT SWITCHING CLOCKING GATE, MEANS FOR CONNECTING SAID CURRENT SWITCHING GATES TO A SOURCE OF DIFFERENTIAL SIGNALS WHICH DIFFERENTIALLY CONTROL THE CONDUCTIVITY OF SAID CURRENT SWITCHING GATES, ONE OF SAID CURRENT SWITCHING REFERENCE AND CLOCKING GATES CONNECTED TO SAID SECOND COMMON NODE AND THE OTHER OF SAID CURRENT SWITCHING REFERENCE AND CLOCKING GATES CONNECTED TO SAID FIRST COMMON NODE, SAID ONE CURRENT SWITCHING GATE OPERATIVELY BIASED INTO CONDUCTION TO MAINTAIN THE MEMORY CIRCUIT IN ITS PREVIOUS CONDUCTIVE STATE WHEN SIGNALS APPLIED THERETO OVERRIDE THE POTENTIAL APPLIED TO SAID OTHER SWITCHING GATE, AND SAID OTHER SWITCHING GATE OPERATIVELY BIASED INTO CONDUCTION WHEN A SIGNAL APPLIED THERETO OVERRIDES THE POTENTIAL ON SAID ONE SWITCHING GATE, SAID OTHER SWITCHING GATE ENABLING THE MEMORY CIRCUIT TO BE SWITCHED FROM ONE OF THE OTHER OF ITS TWO STABLE STATES BY INPUT SIGNALS APPLIED TO SAID FIRST AND SECOND PRESET GATES, INPUT TERMINAL MEANS FOR CONNECTING SAID FIRST AND SECOND PRESET GATES, RESPECTIVELY, TO THE OUTPUT TERMINALS OF THE PRIOR MEMORY STAGE, SAID INPUT TERMINAL MEANS CONNECTED TO EACH OF SAID FIRST AND SECOND PRESET GATES FOR RECEIVING BINARY INPUT SIGNALS THAT OVERRIDE THE POTENTIALS ON SAID FIRST AND SECOND CURRENT SWITCHING MEANS AND CHANGE THE CONDUCTTIVE STATE OF SAID MEMORY CIRCUIT.