Cryoelectric memory system

Claim 1

A CRYOELECTRIC MEMORY SYSTEM COMPRISING: P MEMORY PLANES, WHERE P IS AN INTEGER; P GROUPS OF B DRIVE LINES, ONE GROUP FOR EACH PLANE, EACH GROUP OF LINES PASSING BACK AND FORTH A PLURALITY OF TIMES OVER ITS PLANE; A PLURALITY OF A DRIVE LINES, EACH SUCH LINE PASSING OVER ALL MEMORY PLANES, AND EACH SUCH LINE CROSSING EACH B LINE AT A PLURALITY OF DIFFERENT LOCATIONS ON EACH PLANE; A PLURALITY OF PERSISTENT CURRENT STORAGE ELEMENTS AT EACH PLANE, ONE AT EACH LOCATION WHERE AN A WIRE CROSSES A B WIRE; AND A PLURALITY OF A SENSE LINES AT EACH PLANE, EACH SUCH SENSE LINE BEING COUPLED ONLY TO THE PERSISTENT CURRENT ELEMENTS ON A PLANE WHICH STORE BITS OF THE SAME SIGNIFICANCE.