Patent US4898934A successfully refreshed from Google Patents.
Patent US3423600A successfully refreshed from Google Patents.
US3423600A
Expired / Lapsed
US
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Time relay and pulse generator circuit
Assignee: Nortel Networks Ltd
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Filing: 1966-08-31
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Granted: 1969-01-21
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Expires: 1986-08-31
Abstract
No abstract record available.
Inventors
- 👤 Bruce G Pringle
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-08 08:27
CPC Classifications
H; H03; H03K; H03K5/00; H03K5/13
Claims Analysis
Total Claims: 2
Claim 1
Independent Claim
166 words
A TIME DELAY AND PULSE GENERATOR CIRCUIT COMPRISING: A TRANSISTOR HAVING A BASE, AN EMITTER AND A COLLECTOR; A DIRECT CURRENT SOURCE OF VOLTAGE; A LOAD CONNECTED BETWEEN THE COLLECOR AND ONE END OF SAID SOURCE OF VOLTAGE; A CAPACITOR CONNECTED BETWEEN THE BASE AND THE OTHER END OF SAID SOURCE OF VOLTAGE; A FIRST RESISTOR CONNECTED BETWEEN THE BASE AND SAID ONE END OF THE SOURCE OF VOLTAGE; SECOND, THRID AND FOURTH RESISTORS CONNECTED IN SERIES ACROSS SAID SOURCE OF VOLTAGE, SAID THIRD RESISTOR BEING LOCATED INTERMEDIATE AND SECOND AND FOURTH RESISTORS; FIRST AND SECOND DIODES CONNECTED IN SERIES AIDING ACROSS SAID THIRD RESISTOR SO AS TO BE NORMALLY BACK-BIASED BY SAID SOURCE OF VOLTAGE; THE JUNCTION OF SAID FIRST AND SECOND DIODES BEING CONNECTED TO THE EMITTER; MEANS RESPONSIVE TO CURRENT FLOW THROUGH SAID LOAD FOR CONNECTING A FIFTH RESISTOR BETWEEN THE EMITTER AND SAID OTHER END OF THE SOURCE OF VOLTAGE, AND ALSO FOR CONNECTING A SIXTH RESISTOR IN PARALLEL WITH SAID CAPACITOR.
Claim 2
Dependent Claim
166 words
A TIME DELAY AND PULSE GENERATOR CIRCUIT COMPRISING: A TRANSISTOR HAVING A BASE, AN EMITTER AND A COLLECTOR; A DIRECT CURRENT SOURCE OF VOLTAGE; A LOAD CONNECTED BETWEEN THE COLLECOR AND ONE END OF SAID SOURCE OF VOLTAGE; A CAPACITOR CONNECTED BETWEEN THE BASE AND THE OTHER END OF SAID SOURCE OF VOLTAGE; A FIRST RESISTOR CONNECTED BETWEEN THE BASE AND SAID ONE END OF THE SOURCE OF VOLTAGE; SECOND, THRID AND FOURTH RESISTORS CONNECTED IN SERIES ACROSS SAID SOURCE OF VOLTAGE, SAID THIRD RESISTOR BEING LOCATED INTERMEDIATE AND SECOND AND FOURTH RESISTORS; FIRST AND SECOND DIODES CONNECTED IN SERIES AIDING ACROSS SAID THIRD RESISTOR SO AS TO BE NORMALLY BACK-BIASED BY SAID SOURCE OF VOLTAGE; THE JUNCTION OF SAID FIRST AND SECOND DIODES BEING CONNECTED TO THE EMITTER; MEANS RESPONSIVE TO CURRENT FLOW THROUGH SAID LOAD FOR CONNECTING A FIFTH RESISTOR BETWEEN THE EMITTER AND SAID OTHER END OF THE SOURCE OF VOLTAGE, AND ALSO FOR CONNECTING A SIXTH RESISTOR IN PARALLEL WITH SAID CAPACITOR.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1972-01-21 | 1972-07-22 | 1973-01-21 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1976-01-21 | 1976-07-22 | 1977-01-21 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1980-01-21 | 1980-07-22 | 1981-01-21 | $7700.00 | Window Closed / Lapsed |