Memory circuit using charge storage diodes

Claim 1

IN A MEMORY ARRAY, A PLURALITY OF ROW SELECTION CONDUCTORS AND A PLURALITY OF COLUMN SELECTION CONDUCTORS, A COMMON WRITE BUS, A PLURALITY OF WORD LINE CIRCUIT EACH ASSOCIATED WITH A CROSSOVER OF A ROW SELECTION CONDUCTOR AND A COLUMN SELECTION CONDUCTOR, EACH OF SAID CIRCUITS INCLUDING A SELECTION DIODE CONNECTED FROM A COLUMN SELECTION CONDUCTOR TO A JUNCTION POINT, A READ CHARGE STORAGE DIODE CONNECTED FROM SAID JUNCTION POINT TO A ROW SELECTION CONDUCTOR, A WRITE CHARGE STORAGE DIODE CONNECTED FROM SAID JUNCTION POINT TO A MEMORY WORD LINE, AND A WRITE IMPEDANCE CONNECTED FROM SAID JUNCTION POINT TO SAID COMMON WRITE BUS, SELECTION MEANS TO ENERGIZE ANY ROW SELECTION CONDUCTOR ANY ANY ONE COLUMN SELECTION CONDUCTOR TO SELECT ONE OF SAID WORD LINE CIRCUITS, READ MEANS TO SUBSEQUENTLY ENERGIZE SAID ONE ROW SELECTION CONDUCTOR TO CAUSE A READ CURRENT THROUGH THE SELECTED WORD LINE IN ONE DIRECTION, AND