Mask generating circuit

Claim 1

A DATA PROCSSING MACHINE COMPRISING AN INSTRUCTION DECODER, MEANS SUPPLYING TO SAID DECODER MACHINE INSTRUCTIONS SPECIFYING THE SIZE AND POSITION OF AN ADJACENT-BIT MASK WINDOW, SAID DECORDER PRODUCING OUTPUT SIGNALS REPRESENTING IN BINARY FORM ON A PLURALITY OF OUTPUT CIRCUITS THE BIT MAGNITUDE OF SAID WINDOW AND THE BIT MAGNITUDE SAID WINDOW POSITION WITH RESPECT TO A RIGHT-ADJUSTED POSITION, A BINARY ADDER COMPUTING THE SUM OF SAID WINDOW MAGNITUDE AND SHIFT SIGNALS, TRANSLATING MEANS SEPARATELY CONVERTING SAID SHIFT SIGNALS AND THE OUTPUT OF SAID ADDER INTO SEPARATE ONE-OUT-OF-M SINGAL REPRESENTATIONS, WHERE M IS THE NUMBER OF BITS IN PROCESSING MACHINE WORD, FOR DEFINING THE BIT POSITIONS IN A PROCESSING MACHINE WORD CORRESPONDING THE THE BEGINNING AND ENDING BITS OF SAID MASK WINDOW,