Fast register control circuit

Claim 1

A CONTROL CIRCUIT FOR A DATA PROCESSOR HAVING A MULTISTAGE DATA REGISTER AND INSTRUCTION MEANS FOR INDICATING THE NUMBER OF POSITIONS WHICH THE BITS IN SAID REGISTER ARE TO BE SHIFTED, SAID CONTROL CIRCUIT COMPRISING A PLURALITY OF GATING PATH MEANS INDIVIDUALLY CONNECTING EACH STAGE IN SAID REGISTER TO OTHER STAGES IN SAID REGISTER A PREDETERMINED NUMBER OF POSITIONS AWAY FROM SAID EACH STAGE, MEANS FOR DECODING THE INFORMATION IN SAID INSTRUCTION MEANS, AND MEANS RESPONSIVE TO SAID DECODING MEANS FOR CONTROLLING THE SEQUENTIAL OPERATIONS OF SAID GATING PATH MEANS IN ACCORDANCE WITH THE INFORMATION IN SAID INSTRUCTION MEANS, SAID CONTROLLING MEANS CONTROLLING THE SIMULTANEOUS OPERATIONS OF ALL GATING PATH MEANS CONNECTED BETWEN STAGES SEPARATED BY THE SAME NUMBER OF STAGES.