Error sensitive binary transmission system wherein four channels are transmitted via one carrier wave

Claim 1

IN A COMMUNICATION SYSTEM EMPLOYING TONE SIGNALS DIVIDED INTO TIME SYNCHRONOUS SEGMENTS WITH EACH SEGMENT CONSTITUTING A PHASOR WHOSE PHASE WITH RESPECT TO THE PHASE OF THE PRECEDING PHASOR IS REPRESENTATIVE OF THE INFORMATION ENCODED THEREIN, AND COMPRISING: RECEIVER MEANS FOR RECEIVING SAID PHASORS AND INCLUDING AN ERROR RATE DETECTING MEANS CONSTRUCTED TO PRODUCE CODED SIGNALS INDICATIVE OF THE ERROR RATE OF THE RECEIVED SIGNAL; TRANSMITTER MEANS FOR GENERATING AND TRANSMITTING SAID PHASORS, SAID TRANSMITTER MEANS COMPRISING: SIGNAL TONE GENERATOR MEANS FOR PRODUCING AN ORIGINAL TONE SIGNAL OF FREQUENCY F1; X AND Y SIGNAL COMPONENT GENERATING MEANS CONSTRUCTED TO RESPOND TO TIME SYNCHRONOUS BINARY CODED SIGNALS SUPPLIED THERETO TO PRODUCE X AND Y QUADRATURE PHASED SIGNAL COMPONENTS OF PREDETERMINED COMBINATIONS OF MAGNITUDES AND POLARITIES FROM THE OUTPUT SIGNAL OF SAID SIGNAL TONE GENERATOR; MEANS FOR COMBINING SAID X AND Y SIGNAL COMPONENTS TO PRODUCE A PHASOR OF FREQUENCY F1 BUT PHASED WITH RESPECT TO SAID ORIGINAL TONE SIGNAL IN ACCORDANCE WITH THE RELATIVE MAGNITUDES OF SAID X AND Y SIGNAL COMPONENTS; A PLURALITY OF INFORMATION CHANNELS EACH CONSTRUCTED TO PRODUCE AN OUTPUT SIGNAL CONSISTING OF DATA BITS; ENCODING MEANS INCLUDING FIRST DATA PROCESSOR MEANS FOR RECEIVING THE DATA FROM SAID PLURALITY OF INFORMATION CHANNELS AND BEING PROGRAMMED TO RESPOND TO THE VARIOUS PERMUTATIONS AND COMBINATIONS OF RECEIVED DATA BITS TO PRODUCE AT THE OUTPUT OF SAID DATA PROCESSOR MEANS A CONTINUING OUTPUT OF SAID TIME SYNCHRONOUS BINARY CODED SIGNALS, ONE BINARY CODED SIGNAL FOR EACH DATA BIT INTERVAL AND DETERMINATIVE OF THE RELATIVE MAGNITUDES OF THE X AND Y COMPONENTS TO BE GENERATED BY SAID X AND Y SIGNAL COMPONENT GENERATING MEANS; SAID X AND Y SIGNAL COMPONENT GENERATING MEANS RESPONSIVE TO SAID TIME SYNCHRONOUS BINARY CODED SIGNALS TO PRODUCE PHASORS, EACH HAVING A PHASE WITH RESPECT TO THE PHASE OF THE IMMEDIATELY PRECEDING PHASOR WHICH PHASE IS REPRESENTATIVE OF ALL DATA BITS SUPPLIED FROM ALL THE INFORMATION CHANNELS SUPPLYING DATA TO SAID DATA PROCESSOR DURING A GIVEN DATA BIT TIME INTERVAL, SAID DATA PROCESSOR MEANS FURTHER BEING PROGRAMMED TO RESPOND TO THE ERROR RATE SIGNAL FROM SAID ERROR RATE DETECTING MEANS TO INCREASE OR DECREASE THE NUMBER OF INFORMATION CHANNELS SUPPLYING INFORMATION THERETO UNTIL SAID ERROR RATE LIES WITHIN PREDETERMINED LIMITS.