Simplified partial double error correction using single error correcting code

Claim 1

IN A DATA PROCESSING MACHINE OF THE TYPE HAVING A DATA CHANNEL FOR SIMULTANEOUS TRANSMISSION OF A PLURALITY OF DATA DESIGNATING MANIFESTATIONS, REFERRED TO HEREINAFTER AS A WORD OF BITS, SAID WORD INCLUDING DATA BITS AND PARITY BITS ARRANGED IN AN ORDERED SEQUENCE IN ACCORDANCE WITH THE WELL-KNOWN HAMMING CODE, SAID WORD BEING ARRANGED IN TWO GROUPS, A FIRST GROUP CONTAINING LOW ORDER BITS AND THE SECOND GROUP CONTAINING HIGH ORDER BITS, A DEVICE FOR CORRECTING CERTAIN DOUBLE ERRORS, COMPRISING: DETECTOR MEANS FOR CHECKING EACH PARITY BIT AND FOR GENERATING A RESPECTIVELY CORRESPONDING ERROR SIGNAL WHEN THE RELATED PARITY BIT INCLUDES AN ERROR; AND DOUBLE ERROR IDENTIFICATION MEANS OPERATIVE IN RESPONSE TO THE ABSENCE OF A FIRST ERROR SIGNAL CONCURRENTLY WITH THE PRESENCE OF A SECOND ERROR SIGNAL TO GENERATE DOUBLE ERROR BIT IDENTIFICATION SIGNALS INDICATIVE OF A PAIR OF DATA BITS WHICH ARE PRESUMED TO BE IN ERROR, SAID SIGNALS BEING SELECTIVELY DIFFERENT IN DEPENDENCE UPON THE PRESENCE OF OTHER ONES OF SAID ERROR SIGNALS, EACH OF SAID DOUBLE ERROR BIT IDENTIFICATION SIGNALS INCLUDING AN ADDRESS RESPECTIVELY CORRESPONDING TO A BIT IN EACH OF SAID GROUPS, SAID FIRST ERROR SIGNAL BEING GENERATED IN RESPONSE TO SAID DETECTOR MEANS DETECTING ERROR IN THE PARITY BIT RELATED TO THE ENTIRE WORD, SAID SECOND ERROR SIGNAL BEING GENERATED IN RESPONSE TO SAID DETECTOR MEANS DETECTING ERROR IN THE PARITY BIT RELATED TO SAID SECOND GROUP.