Simplified error-control decoder

Claim 1

IN DATA PROCESSING APPARATUS THAT PROCESSES CODE WORDS HAVING N BINARY DIGIT SIGNALS IN N RESPECTIVE POSITIONS IN THE WORD, OF WHICH K SIGNALS REPRESENT INFORMATION BITS, A DECODER COMPRISING: (A) A REGISTER ADAPTED TO RECEIVE THE CODE WORD SIGNALS IN SUCH A MANNER THAT THE BITS OF THE CODE WORD SIGNALS ARE ENTERED INTO POSITIONS OF THE REGISTER CORRESPONDING TO THEIR POSITION IN THE CODE WORD; (B) CYCLIC ESTIMATIION LOGIC CIRCUITS WHICH OPERATE AS A FUNCTION OF THE RECEIVED BITS IN SAID REGISTER IN A MANNER TO PROVIDE THE REQUIRED NUMBER OF ESTIMATE SIGNALS BY INDEPENDENT VALUE ESTIMATES OF THE CORRERECT VALUE OF THE RECEIVED BIT IN A SPECIFIC POSITION OF THE REGISTER; (C) A DECISION LOGIC CIRCUIT RESPONSIVE TO THE ESTIMATE SIGNALS TO PROVIDE DECODED OUTPUT BIT SIGNAL IN ACCORDANCE WITH THE MAJORITY OF THE ESTIMATE SIGNALS; AND (D) CONTROL CIRCUITRY TO CYCLICALLY SHIFT THE BIT SIGNALS IN SAID REGISTER FOR K BIT DECODING OPERATIONS, TO INITIATE A BIT DECODING OPERATIION AFTER EACH SHIFT, AND TO TERMINATE WORD DECODING OPERATIONS AFTER K BIT DECODING OPERATIONS.